Three-dimensional memory devices, systems, and methods for forming the same

1 . A three-dimensional (3D) memory device, comprising:

a stack comprising a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, wherein the stack comprises a staircase structure;

an insulating structure over the stack and the staircase structure;

a plurality of contact structures each extending through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure;

a plurality of support structures extending through the stack in the staircase structure;

a first semiconductor layer under the stack;

a second semiconductor layer under the first semiconductor layer; and

a channel structure extending through the stack and in contact with the second semiconductor layer,

wherein the plurality of contact structures are arranged in a first row and a second row along a first direction, the first row is adjacent and parallel to the second row, the first row of the plurality of contact structures is in electrical contact with a peripheral device, and the second row of the plurality of contact structures is in electrical insulation with the peripheral device;

wherein one or more than one adjacent level of the staircase structure is vertically offset by a nominally same distance in the first direction;

wherein the plurality of support structures extend through the first semiconductor layer and extend into the second semiconductor layer; and

wherein the first semiconductor layer and the channel structure are separated by the second semiconductor layer.

2 . The 3D memory device of claim 1 , wherein each of the plurality of contact structures further comprises a staircase contact in contact with the respective conductive layer of the plurality of conductive layers.

3 . The 3D memory device of claim 2 , wherein the staircase contact is disposed between the plurality of contact structures and the plurality of support structures.

4 . The 3D memory device of claim 3 , wherein the plurality of contact structures and the plurality of support structures overlap in a plan view of the 3D memory device.

5 . The 3D memory device of claim 4 , wherein each of the plurality of support structures aligns one of the plurality of contact structures.

6 . The 3D memory device of claim 1 , wherein the plurality of contact structures and the plurality of support structures comprise different materials.

7 . The 3D memory device of claim 6 , wherein the plurality of support structures comprise a dielectric material.

8 . The 3D memory device of claim 7 , wherein the plurality of contact structures comprise a conductive material.

9 . The 3D memory device of claim 1 , wherein the first semiconductor layer and the plurality of contact structures are separated by at least one of the plurality of conductive layers.

10 . The 3D memory device of claim 3 , wherein each of the plurality of contact structures comprises a first end away from the staircase contact and a second end near the staircase contact, and a width of the first end is greater than a width of the second end.

11 . The 3D memory device of claim 10 , wherein each of the plurality of support structures comprises a third end near the staircase contact and a fourth end away from the staircase contact, and a width of the third end is greater than a width of the fourth end.

12 . The 3D memory device of claim 11 , wherein the width of the first end is greater than the width of the third end.

13 . A system, comprising:

a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:

a stack in an insulating structure comprising a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, wherein the stack comprises a staircase structure;

a plurality of contact structures each extending through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure;

a plurality of support structures extending through the stack in the staircase structure;

a first semiconductor layer under the stack;

a second semiconductor layer under the first semiconductor layer; and

a channel structure extending through the stack and in contact with the second semiconductor layer; and

a memory controller coupled to the 3D memory device and configured to control operations of the 3D memory device,

wherein the plurality of contact structures are arranged in a first row and a second row along a first direction, the first row is adjacent and parallel to the second row, the first row of the plurality of contact structures is in electrical contact with a peripheral device, and the second row of the plurality of contact structures is in electrical insulation with the peripheral device;

wherein one or more than one adjacent level of the staircase structure is vertically offset by a nominally same distance in the first direction;

wherein the plurality of support structures extend through the first semiconductor layer and extend into the second semiconductor layer; and

wherein the first semiconductor layer and the channel structure are separated by the second semiconductor layer.

14 . The 3D memory device of claim 1 , wherein the first row and the second row extend along a same direction with a height decreasing direction of the staircase structure.

15 . The system of claim 13 , wherein the first row and the second row extend along a same direction with a height decreasing direction of the staircase structure.

16 . The system of claim 13 , wherein each of the plurality of contact structures further comprises a staircase contact in contact with the respective conductive layer of the plurality of conductive layers.

17 . The system of claim 16 , wherein the staircase contact is disposed between the plurality of contact structures and the plurality of support structures.

18 . The system of claim 17 , wherein the plurality of contact structures and the plurality of support structures overlap in a plan view of the 3D memory device.

19 . The system of claim 18 , wherein each of the plurality of support structures aligns one of the plurality of contact structures.