Solderable and wire bondable part marking
View Patent ↗A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.
1 . A semiconductor device, comprising:
a doped polysilicon layer;
a terminal comprising a top metal layer formed on the doped polysilicon layer; and
an identifier provided on the top metal layer of the terminal, wherein the identifier comprises an optically-contrasting mark relative to the top metal layer of the terminal, and wherein the identifier comprises a patterned layer of metal that maintains solderability and wire bondability of the top metal layer when the top metal layer is bonded with a conductor.
2 . The semiconductor device of claim 1 , wherein the terminal is at least one of gold, copper, silver, or aluminum.
3 . The semiconductor device of claim 1 , wherein the identifier is deposited on the terminal via at least one of evaporation, a lift-off process, etching, sputtering, or plating, and wherein the semiconductor device further comprises:
a silicon nitride layer deposited around the top metal layer; and
a benzocyclobutene layer deposited around the top metal layer.
4 . The semiconductor device of claim 3 , wherein the semiconductor device is configured to operate at 1,000 volts or more, and wherein the identifier is exposed through a gap in at least one of the silicon nitride layer and the benzocyclobutene layer.
5 . The semiconductor device of claim 1 , wherein the patterned layer of metal comprises a patterned layer of palladium.
6 . The semiconductor device of claim 5 , wherein the patterned layer of palladium forms one or more lines of alphanumeric text or a symbol on the terminal and provides at least some information describing the semiconductor device.
7 . The semiconductor device of claim 6 , wherein at least a portion of the terminal is exposed through a gap in the patterned layer of palladium.
8 . The semiconductor device of claim 1 , wherein the semiconductor device is one of a capacitor, a diode, a transistor, a thyristor, a resistor, an inductor, or a filter.
9 . The semiconductor device of claim 1 , wherein the identifier comprises at least 75% by weight palladium.
10 . The semiconductor device of claim 1 , wherein the identifier comprises at least 95% by weight palladium.
11 . The semiconductor device of claim 1 , wherein the identifier provides information that uniquely describes the semiconductor device.
12 . A semiconductor device, comprising:
a doped polysilicon layer; and
an electrical contact comprising a top metal layer formed on the doped polysilicon layer by a first metallization process and comprising one or more identifiers formed by a second metallization process on the top metal layer of the electrical contact, wherein the one or more identifiers comprise an optically-contrasting mark relative to the top metal layer of the electrical contact, and wherein the one or more identifiers comprise a patterned layer of metal that maintain solderability and wire bondability of the top metal layer when the top metal layer is bonded with a conductor.
13 . The semiconductor device of claim 12 , wherein the one or more identifiers further maintain an intrinsic capacitance and breakdown voltage capability of the electrical contact.
14 . The semiconductor device of claim 12 , wherein the electrical contact is made of at least one of gold, copper, silver, or aluminum.
15 . The semiconductor device of claim 12 , wherein the second metallization process deposits a layer of palladium on the top metal layer using at least one of evaporation, a lift-off process, etching, sputtering, or plating.
16 . The semiconductor device of claim 12 , wherein the patterned layer of metal comprises a layer of palladium, and wherein the one or more identifiers comprise one or more lines of alphanumeric text or a symbol and provide at least some information describing the semiconductor device.
17 . The semiconductor device of claim 16 , wherein at least a portion of the electrical contact is exposed through a gap in the layer of palladium.
18 . The semiconductor device of claim 12 , wherein the semiconductor device is one of a capacitor, a diode, a transistor, a thyristor, a resistor, an inductor, or a filter.
19 . The semiconductor device of claim 12 , wherein the semiconductor device is configured to operate at 1,000 volts or more, and wherein the one or more identifiers are exposed through a gap in at least one of a silicon nitride layer and a benzocyclobutene layer.
20 . A semiconductor device manufactured by a process comprising:
depositing, on a top surface of a silicon substrate, a dielectric layer;
depositing, on a top surface of the dielectric layer, a doped polysilicon layer;
performing a first metallization process on a semiconductor device in production that yields at least one electrical terminal on the semiconductor device; and
performing a second metallization process that deposits an identifier on a top metal layer of an electrical terminal of the at least one electrical terminal, wherein the identifier comprises an optically-contrasting mark relative to the top metal layer of the electrical terminal, and wherein the identifier comprises a patterned layer of metal that maintains solderability and wire bondability of the top metal layer when the top metal layer is bonded with a conductor.