IP Library › Granted Patent US 12690469
Granted Patent B2
US 12690469 · App. 17/818,778 · Granted Jul 21, 2026

Packaged semiconductor device, leadframe and method for improved bonding

Inventors: You Ge (Tianjin, CN); Zhijie Wang (Tianjin, CN); Yit Meng Lee (Kuala Lumpur, MY); Yanbo Xu (Tianjin, CN)
Assignee: NXP USA, Inc.
H10W70/417H10W72/07332H10W72/354H10W72/884H10W90/736H10W90/756
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Quick Facts
Patent No.
US 12690469
App. No.
17/818,778
Granted
Jul 21, 2026
Kind
B2
Abstract

There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.

Claims (34)

1 . A packaged semiconductor device comprising:

a leadframe having a first thickness; the leadframe comprising a die pad;

a semiconductor die thereabove; and

epoxy therebetween and arranged to bond the semiconductor die to the die pad;

wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness;

wherein the die pad has at least one through-hole in the at least one region; and

wherein the epoxy fills the at least one through-hole to form at least one plug that extends thereunder the at least one region and laterally beyond the through-hole.

2 . The packaged semiconductor device of claim 1 , wherein the epoxy has a thermal conductivity of at least 10 W/m·K.

3 . The packaged semiconductor device of claim 2 wherein the second thickness is within a range of 40% to 60% of the first thickness.

4 . The packaged semiconductor device of claim 1 , wherein the at least one region extends laterally beyond the semiconductor die.

5 . The packaged semiconductor device of claim 4 wherein the second thickness is within a range of 40% to 60% of the first thickness.

6 . The packaged semiconductor device of claim 1 , wherein the at least one region comprises a network of elongate channels.

7 . The packaged semiconductor device of claim 6 , wherein the network of elongate channels extends radially from a hub.

8 . The packaged semiconductor device of claim 6 , wherein the at least one region extends laterally beyond the semiconductor die.

9 . The packaged semiconductor device of claim 1 , wherein the leadframe further comprises a plurality of leads, electrically isolated from the die pad.

10 . The packaged semiconductor device of claim 1 , further comprising a moulding compound encapsulating the semiconductor die.

11 . The packaged semiconductor device of claim 1 configured as a quad-flat-no-lead, QFN, package.

12 . The packaged semiconductor device of claim 1 wherein the second thickness is within a range of 40% to 60% of the first thickness.

13 . The packaged semiconductor device of claim 1 wherein the at least one through-hole includes a plurality of through-holes.

14 . The packaged semiconductor device of claim 13 wherein the at least one plug includes a plurality of plugs, wherein each plug of the plurality of plugs includes a portion located in a through-hole of the plurality of through-holes.

15 . The packaged semiconductor device of claim 1 wherein each plug of the at least one plug includes a first portion located in a through-hole of the at least one through-hole and a head portion that is located under the first portion,

wherein the head portion is wider than the body portion.

16 . The packaged semiconductor device of claim 15 wherein for each plug of the at least one plug, the head portion is wider than a diameter of a through-hole of the at least one through-hole that the first portion of the each plug is located in.

17 . The packaged semiconductor device of claim 1 wherein:

a top surface of the at least one region of the die pad is coplanar with a top surface of other regions of the die pad;

a bottom surface of the at least one region of the die pad is located closer to the top surface of the at least one region than a bottom surface of the other regions of the die pad are located to the top surface of the other regions.

18 . The packaged semiconductor device of claim 1 , wherein:

the at least one region comprises a network of at least two elongate channels;

each elongate channel of the network includes at least one through-hole of the at least one through-hole where each through-hole includes a portion of a plug of the at least one plug.

19 . An assembly including the packaged semiconductor device of claim 1 ,

wherein the assembly further comprises:

a circuit board, wherein the packaged semiconductor devices is mounted on the circuit board;

solder located between the circuit board and the packaged semiconductor device, wherein the solder is in contact with the at least one plug.

20 . The assembly of claim 19 wherein the solder is in contact with an underside surface of the at least one region.