IP Library Granted Patent US 12690471
Granted Patent B2
US 12690471 · App. 18/474,325 · Granted Jul 21, 2026

Semiconductor device for upper and lower arm circuits

Inventors: Takahiro Hirano (Kariya-city, JP); Masayoshi Nishihata (Kariya-city, JP); Chihiro Kato (Kariya-city, JP)
Assignee: DENSO CORPORATION
H10W70/464H10W90/00H10W90/811H10W70/481H10W72/631H10W72/652H10W72/655H10W90/763H10W90/766H10W90/767
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12690471
App. No.
18/474,325
Granted
Jul 21, 2026
Kind
B2
Abstract

A semiconductor device includes: a first element for one of upper and lower arm circuits; a second element for the other of the upper and lower arm circuits; a first wiring having a first mounting portion on which the first element is disposed and a first power supply terminal portion connected with the first mounting portion; a second wiring having a second mounting portion on which the second element is disposed and an output terminal portion connected with the second mounting portion; a clip configured to electrically connect a main electrode of the first element and the second mounting portion; and a third wiring having a connection portion to which a main electrode of the second element is connected and a second power supply terminal portion connected with the connection portion. The third wiring is extended parallel to the first wiring and the clip.

Claims (28)

1 . A semiconductor device for upper and lower arm circuits of at least one phase, comprising:

a plurality of semiconductor elements including a first element for one arm of the upper and lower arm circuits and a second element for another arm of the upper and lower arm circuits, each having a first main electrode provided on one surface and a second main electrode provided on a back surface opposite to the one surface in a thickness direction;

a first wiring having a first mounting portion on which the first element is disposed and to which a first main electrode of the first element is connected, and a first power supply terminal portion connected to the first mounting portion;

a second wiring having a second mounting portion on which the second element is disposed and to which a first main electrode of the second element is connected, and an output terminal portion continuous with the second mounting portion, the first mounting portion and the second mounting portion being arranged in one direction orthogonal to the thickness direction;

a clip configured to electrically connect the second main electrode of the first element and the second mounting portion; and

a third wiring having a connection portion to which a second main electrode of the second element is connected and a second power supply terminal portion connected to the connection portion, wherein

the third wiring extends parallel to the first wiring and the clip, and

the third wiring faces the first wiring and the clip in a width direction orthogonal to both the one direction and the thickness direction.

2 . The semiconductor device according to claim 1 , wherein

the clip is a first clip, and

the third wiring includes

a second clip including the connection portion, and

a terminal including the second power supply terminal portion and connected to the second clip.

3 . The semiconductor device according to claim 1 , wherein

the first wiring, the clip, and the third wiring extend in the one direction in a plan view.

4 . The semiconductor device according to claim 1 , wherein

a first part of the third wiring and a part of the first wiring are arranged in the width direction,

a second part of the third wiring and a part of the clip are arranged in the width direction, and

the third wiring faces each of the first wiring and the clip in the width direction over a predetermined length in the one direction.

5 . The semiconductor device according to claim 1 , wherein

the third wiring has two extending portions extending in the one direction,

the first wiring and the clip are interposed between the two extending portions in the width direction, and

a part of the first wiring interposed between the two extending portions and a part of the clip interposed between the two extending portions are arranged in the one direction in a plan view.

6 . The semiconductor device according to claim 1 , wherein

the third wiring has two extending portions extending in the one direction, and

the clip is interposed between the two extending portions in the width direction.

7 . The semiconductor device according to claim 6 , wherein

a thickness of the extending portions is equal to a thickness of the clip.