Wiring substrate, semiconductor device, and method of manufacturing wiring substrate

1 . A wiring substrate, comprising:

a first wiring substrate;

a plurality of second wiring substrates arranged adjacent to each other on the first wiring substrate; and

an adhesive layer that adheres the first wiring substrate and the plurality of second wiring substrates to each other,

wherein

each of the plurality of second wiring substrates has a wiring structure including a plurality of wiring layers and a plurality of insulating layers stacked over each other alternately, each of the plurality of insulating layers being composed of insulating resin,

the adhesive layer has a filling portion that fills a groove portion formed by facing of side surfaces of adjacent ones of the plurality of second wiring substrates,

the filling portion has an end face positioned in a same plane as an upper surface of an uppermost insulating layer of the plurality of insulating layers included in the wiring structure of each of the adjacent ones of the plurality of second wiring substrates,

the adhesive layer has a covering portion that covers a part of side surfaces of the adjacent ones of the plurality of second wiring substrates, the side surfaces not facing each other, and

the end face is higher from the first wiring substrate than an uppermost end of the covering portion.

2 . The wiring substrate according to claim 1 , wherein the adhesive layer has a thermal expansion coefficient lower than that of the insulating resin forming each of the plurality of insulating layers of the wiring structure of each of the plurality of second wiring substrates.

3 . The wiring substrate according to claim 2 , wherein the thermal expansion coefficient of the insulating resin is 40 to 70 (ppm/° C.), and

the thermal expansion coefficient of the adhesive layer is 20 to 40 (ppm/° C.).

4 . The wiring substrate according to claim 1 , wherein the adhesive layer adheres the first wiring substrate and the plurality of second wiring substrates to each other in a state of covering at least a part of side surfaces of the adjacent ones of the plurality of second wiring substrates, the side surfaces not facing each other.

5 . The wiring substrate according to claim 4 , wherein the adhesive layer has another filling portion that fills a space between the first wiring substrate and the plurality of second wiring substrates, and

the filling portion, the another filling portion, and the covering portion are integrally formed.

6 . The wiring substrate according to claim 1 , wherein

the first wiring substrate has a first electrode pad on a surface opposed to each of the plurality of second wiring substrates,

each of the plurality of second wiring substrates has a second electrode pad on a surface opposed to the first wiring substrate, and

the first electrode pad and the second electrode pad are connected by a solder.

7 . The wiring substrate according to claim 1 , wherein the adhesive layer has an elastic modulus higher than that of the insulating resin forming each of the plurality of insulating layer layers of the wiring structure of each of the plurality of second wiring substrates.

8 . The wiring substrate according to claim 7 , wherein the elastic modulus of the insulating resin is 2 to 4 (GPa), and

the elastic modulus of the adhesive layer is 6 to 9 (GPa).

9 . The wiring substrate according to claim 1 , wherein the end face is positioned in the same plane as the upper surface of the uppermost insulating layer, the same plane being lower than an upper surface of an uppermost wiring layer of the plurality of wiring layers included in the wiring structure of each of the adjacent ones of the plurality of second wiring substrates.

10 . A semiconductor device, comprising:

a wiring substrate; and

a semiconductor chip mounted on the wiring substrate,

wherein the wiring substrate comprises:

a first wiring substrate;

a plurality of second wiring substrates arranged adjacent to each other on the first wiring substrate; and

an adhesive layer that adheres the first wiring substrate and the plurality of second wiring substrates to each other,

wherein

each of the plurality of second wiring substrates has a wiring structure including a plurality of wiring layers and a plurality of insulating layers stacked over each other alternately, each of the plurality of insulating layers being composed of insulating resin,

the adhesive layer has a filling portion that fills a groove portion formed by facing of side surfaces of adjacent ones of the plurality of second wiring substrates, and

the filling portion has an end face positioned in a same plane as an upper surface of an uppermost insulating layer of the plurality of insulating layers included in the wiring structure of each of the adjacent ones of the plurality of second wiring substrates,

the adhesive layer has a covering portion that covers a part of side surfaces of the adjacent ones of the plurality of second wiring substrates, the side surfaces not facing each other, and

the end face is higher from the first wiring substrate than an uppermost end of the covering portion.

11 . The semiconductor device according to claim 10 , wherein

the semiconductor chip is mounted across the upper surfaces of the adjacent ones of the plurality of second wiring substrates and the end face of the filling portion.

12 . The semiconductor device according to claim 11 , further comprising an underfill resin that is disposed between the plurality of second wiring substrates and the semiconductor chip, covers the upper surfaces of the adjacent ones of the plurality of second wiring substrates and the end face of the filling portion, and does not enter the groove.

13 . The semiconductor device according to claim 10 , wherein the end face is positioned in the same plane as the upper surface of the uppermost insulating layer, the same plane being lower than an upper surface of an uppermost wiring layer of the plurality of wiring layers included in the wiring structure of each of the adjacent ones of the plurality of second wiring substrates.