IP Library Granted Patent US 12690475
Granted Patent B2
US 12690475 · App. 17/478,439 · Granted Jul 21, 2026

Lithography pillar process for embedded bridge scaling

Inventors: Kyle McElhinny (Tempe, AZ); Haobo Chen (Gilbert, AZ); Hongxia Feng (Chandler, AZ); Xiaoying Guo (Chandler, AZ); Leonel Arana (Phoenix, AZ)
Assignee: Intel Corporation
H10W70/65H10W70/093H10W70/611H10W70/635H10W90/00H10W90/701H10W72/07252H10W72/221
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12690475
App. No.
17/478,439
Granted
Jul 21, 2026
Kind
B2
Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate, and a first pad over the package substrate. In an embodiment, a layer is over the package substrate, where the layer is an insulating material. In an embodiment, the electronic package further comprises a via through the layer and in contact with the first pad. In an embodiment a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width. In an embodiment, the electronic package further comprises a second pad over the via.

Claims (32)

1 . An electronic package, comprising:

a package substrate;

a first pad over the package substrate;

a layer over the package substrate, wherein the layer is an insulating material;

a via through the layer and in contact with the first pad, wherein a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width;

a second pad over the via, wherein there is no seam at the interface between the via and the second pad;

a third pad over the package substrate;

a second via through the layer and contacting the third pad; and

a fourth pad over the second via, wherein the fourth pad is substantially similar to the second pad, and wherein a distance between the fourth pad and the second pad is approximately 10 μm or smaller.

2 . The electronic package of claim 1 , wherein a sidewall of the via is tapered.

3 . The electronic package of claim 1 , wherein a width of the second pad is approximately 10 μm or smaller.

4 . The electronic package of claim 1 , wherein the first pad is electrically coupled to a bridge embedded in the package substrate.

5 . The electronic package of claim 1 , wherein a sidewall of the via is smooth.

6 . The electronic package of claim 1 , further comprising:

a solder over the second pad.

7 . The electronic package of claim 1 , wherein the second via has a width that is greater than a width of the via.

8 . An electronic package, comprising:

a package substrate;

a first pad over the package substrate;

a layer over the package substrate, wherein the layer is an insulating material;

a via through the layer and in contact with the first pad, wherein a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width;

a second pad over the via;

a third pad over the package substrate;

a second via through the layer and contacting the third pad; and

a fourth pad over the second via, wherein the fourth pad is substantially similar to the second pad, and wherein a distance between the fourth pad and the second pad is approximately 10 μm or smaller.

9 . The electronic package of claim 8 , wherein a sidewall of the via is tapered.

10 . The electronic package of claim 8 , wherein a width of the second pad is approximately 10 μm or smaller.

11 . The electronic package of claim 8 , wherein the first pad is electrically coupled to a bridge embedded in the package substrate.

12 . The electronic package of claim 8 , wherein a sidewall of the via is smooth.

13 . The electronic package of claim 8 , further comprising:

a solder over the second pad.

14 . The electronic package of claim 8 , wherein the second via has a width that is greater than a width of the via.