Semiconductor device package and methods of formation
An adhesion layer may be formed over portions of a redistribution layer (RDL) in a redistribution structure of a semiconductor device package. The portions of the RDL over which the adhesion layer is formed may be located in the “shadow” of (e.g., the areas under and/or over and within the perimeter of) one or more through insulator layers (TIVs) that are connected with the redistribution layer structure. The adhesion layer, along with a seed layer on which the portions of the RDL are formed, encapsulate the portions of the RDL in the shadow of the one or more TIVs, which promotes and/or increases adhesion between the portions of the RDL and the polymer layers of the redistribution structure.
1 . A semiconductor device package, comprising:
a redistribution structure comprising one or more dielectric layers including a plurality of metallization layers;
a plurality of interconnect structures connected to a first metallization layer, of the plurality of metallization layers and at a first side of the redistribution structure,
wherein a first portion, of a second metallization layer of the plurality of metallization layers and that is over an entirety of an interconnect structure of the plurality of interconnect structures, is surrounded by an adhesion layer between the first portion of the second metallization layer and the one or more dielectric layers,
wherein the first portion of the second metallization layer is at a second side of the redistribution structure opposing the first side; and
a semiconductor die package below the first side of the redistribution structure,
wherein the adhesion layer is omitted from a second portion, of the second metallization layer, that is over the semiconductor die package.
2 . The semiconductor device package of claim 1 , wherein the first portion of the second metallization layer extends laterally outward from a perimeter of the interconnect structure such that the adhesion layer that surrounds the first portion of the second metallization layer extends laterally outward from the perimeter of the interconnect structure.
3 . The semiconductor device package of claim 1 , wherein the second metallization layer is a topmost redistribution layer (RDL) layer in the redistribution structure; and
wherein the first metallization layer is a bottommost RDL layer in the redistribution structure.
4 . The semiconductor device package of claim 1 , wherein the second portion of the second metallization layer is in direct contact with the one or more dielectric layers.
5 . The semiconductor device package of claim 1 , wherein the plurality of interconnect structures are located in a through insulator via (TIV) region of the semiconductor device package; and
wherein the first portion of the second metallization layer is included in the TIV region of the semiconductor device package.
6 . The semiconductor device package of claim 1 , wherein the adhesion layer is included between the first portion of the second metallization layer and a seed layer of a via structure; and
wherein the via structure is included between the interconnect structure and the first portion of the second metallization layer.
7 . The semiconductor device package of claim 6 , wherein the adhesion layer and the seed layer include a same material.
8 . A semiconductor device package, comprising:
a first redistribution structure;
a second redistribution structure comprises a redistribution layer (RDL) at a first side of the second redistribution structure;
a semiconductor die package, between the first redistribution structure and the second redistribution structure, connected with the first redistribution structure; and
a plurality of through insulator vias (TIVs) extending between the first redistribution structure and a second side of the second redistribution structure opposing the first side,
wherein a first portion of the RDL is over the plurality of TIVs and surrounded by a titanium layer, wherein the titanium layer is omitted from a second portion of the RDL.
9 . The semiconductor device package of claim 8 , further comprising:
a backside enhance layer (BEL) film above the second side of the second redistribution structure.
10 . The semiconductor device package of claim 9 , wherein the first portion of the RDL is connected with solder bumps that extend partially through the BEL film.
11 . The semiconductor device package of claim 8 , wherein subsets of the plurality of TIVs are included in respective TIV regions of the semiconductor device package; and
wherein subsets of the first portion of the RDL are included in the respective TIV regions of the semiconductor device package.
12 . The semiconductor device package of claim 8 , wherein second portion of the RDL is in direct contact with a polymer layer of the second redistribution structure.
13 . A semiconductor device package, comprising:
a redistribution structure, comprising:
a first polymer layer over a carrier substrate,
a first redistribution layer (RDL) over the first polymer layer,
an adhesion layer over the first polymer layer and on a first portion of the first RDL, wherein the adhesion layer is omitted from a second portion of the first RDL,
one or more second polymer layers above the first RDL, and
one or more second RDLs above the first RDL; and
a plurality of through insulator vias (TIVs) on the redistribution structure,
wherein the plurality of TIVs are connected to at least one of the one or more second RDLs.
14 . The semiconductor device package of claim 13 , wherein the first portion of the first RDL are under the plurality of TIVs.
15 . The semiconductor device package of claim 13 , wherein the adhesion layer comprises titanium (Ti).
16 . The semiconductor device package of claim 13 , wherein a second polymer layer of the one or more second polymer layers is on the adhesion layer, wherein the adhesion layer is configured to promote adhesion between the first portion of the first RDL and the second polymer layer.
17 . The semiconductor device package of claim 13 , further comprising:
a first seed layer on the first polymer layer,
wherein the first RDL is formed on the first seed layer, and
wherein the adhesion layer and the first seed layer encapsulate the first portion of the first RDL.
18 . The semiconductor device package of claim 17 , further comprising:
a second seed layer on a portion of the adhesion layer that is one of at least one of the first portion of the first RDL.
19 . The semiconductor device package of claim 18 , further comprising:
a via structure on the second seed layer.
20 . The semiconductor device package of claim 17 , wherein the adhesion layer and the first seed layer include a same material.