Semiconductor package having semiconductor chip on wiring layers and method of fabricating the same
A semiconductor package includes stacked wiring layers, a lower substrate pad on a bottom surface of a lowermost wiring layer, a protection layer covering the lower substrate pad on the bottom surface of the lowermost wiring layer, a dielectric layer on a top surface of an uppermost wiring layer, an upper substrate pad on the dielectric layer, a semiconductor chip on the upper substrate pad, and a molding layer covering the semiconductor chip on the uppermost wiring layer. Each of the wiring layers includes a dielectric pattern and a wiring pattern therein. The protection layer has openings that expose the lower substrate pad. A thickness of the dielectric layer is less than that of the dielectric pattern in the wiring layers. A thickness of the upper substrate pad is less than that of the wiring pattern in the wiring layers.
1 . A semiconductor package, comprising:
wiring layers that are sequentially stacked;
a lower substrate pad on a bottom surface of a lowermost one of the wiring layers;
a protection layer on the bottom surface of the lowermost one of the wiring layers, the protection layer covering a first portion of the lower substrate pad, and the protection layer including an opening exposing a second portion of the lower substrate pad;
a dielectric layer on a top surface of an uppermost one of the wiring layers;
an upper substrate pad on the dielectric layer;
a semiconductor chip on the upper substrate pad; and
a molding layer on the uppermost one of the wiring layers, the molding layer covering the semiconductor chip,
wherein each of the wiring layers includes:
a dielectric pattern, a thickness of the dielectric layer being less than a thickness of the dielectric pattern; and
a wiring pattern in the dielectric pattern, a thickness of the upper substrate pad being less than a thickness of the wiring pattern,
wherein the semiconductor chip comprises a chip pad at a bottom surface of the semiconductor chip, and
wherein the chip pad is electrically connected to the upper substrate pad.
2 . The semiconductor package as claimed in claim 1 , wherein:
the wiring pattern of each of the wiring layers includes:
a head portion in the dielectric pattern; and
a tail portion on the head portion, the tail portion penetrating the dielectric pattern, and
the thickness of the wiring pattern in the uppermost one of the wiring layers corresponds to a thickness of the head portion in the uppermost one of the wiring layers.
3 . The semiconductor package as claimed in claim 2 , wherein the tail portion of the wiring pattern included in the uppermost one of the wiring layers penetrates the dielectric pattern and contacts a bottom surface of the upper substrate pad.
4 . The semiconductor package as claimed in claim 2 , wherein a width of the tail portion of the wiring pattern in the uppermost one of the wiring layers is in a range of about 30 μm to about 60 μm.
5 . The semiconductor package as claimed in claim 1 , wherein:
the upper substrate pad is on a top surface of the dielectric layer,
the lower substrate pad is buried in the protection layer, and
a bottom surface of the lower substrate pad is exposed by a recess on the protection layer.
6 . The semiconductor package as claimed in claim 1 , wherein:
the thickness of the dielectric layer is in a range of about 1 μm to about 4 μm, and
the thickness of the dielectric pattern in each of the wiring layers is in a range of about 10 μm to about 40 μm.
7 . The semiconductor package as claimed in claim 1 , wherein:
the thickness of the upper substrate pad is in a range of about 1 μm to about 5 μm, and
the thickness of the wiring pattern in the wiring layers is in a range of about 5 μm to about 20 μm.
8 . The semiconductor package as claimed in claim 1 , wherein the dielectric layer includes a material different from a material of the protection layer and from a material of the dielectric pattern in the wiring layers.
9 . The semiconductor package as claimed in claim 8 , wherein:
the dielectric layer includes one or more of perylene and silicon nitride, and
the wiring layers and the protection layer include a photo-imageable dielectric or a dielectric polymer.
10 . The semiconductor package as claimed in claim 1 , wherein the upper substrate pad has:
a mesa shape having a width decreasing with an increasing distance from the dielectric layer; or
a pillar shape with a constant width.
11 . The semiconductor package as claimed in claim 1 , further comprising a plating layer on the upper substrate pad.
12 . The semiconductor package as claimed in claim 1 ,
wherein the chip pad is electrically connected to the upper substrate pad by a chip connection terminal.
13 . The semiconductor package as claimed in claim 12 ,
wherein the chip connection terminal is between the chip pad and the upper substrate pad.
14 . A semiconductor package, comprising:
a wiring substrate;
a semiconductor chip on the wiring substrate; and
a molding layer on the wiring substrate, the molding layer covering the semiconductor chip,
wherein the wiring substrate includes:
dielectric patterns that are sequentially stacked;
wiring patterns in the dielectric patterns;
a dielectric layer covering a top surface of an uppermost one of the dielectric patterns, a thickness of the dielectric layer being less than a thickness of each of the dielectric patterns, and the thickness of the dielectric layer being in a range of about 1 μm to about 4 μm;
an upper substrate pad on the dielectric layer;
lower substrate pads on a bottom surface of a lowermost one of the dielectric patterns; and
a protection layer on the bottom surface of the lowermost one of the dielectric patterns, the protection layer covering first portions of the lower substrate pads, and the protection layer including openings exposing second portions of the lower substrate pads,
wherein the semiconductor chip comprises a chip pad at a bottom surface of the semiconductor chip, and
wherein the chip pad is electrically connected to the upper substrate pad.
15 . The semiconductor package as claimed in claim 14 , wherein the wiring patterns include:
a head portion in one of the dielectric patterns, the head portion constituting a horizontal wiring line; and
a tail portion connected to a top surface of the head portion, the tail portion penetrating one of the dielectric patterns and contacts an adjacent one of the wiring patterns.
16 . The semiconductor package as claimed in claim 15 , wherein the tail portion of an uppermost one of the wiring patterns penetrates the dielectric layer and contacts the upper substrate pads.
17 . The semiconductor package as claimed in claim 14 , wherein:
the upper substrate pads extend onto a top surface of the dielectric layer, and
the lower substrate pads are buried within the protection layer.
18 . The semiconductor package as claimed in claim 14 , wherein the thickness of each of the dielectric patterns is in a range of about 10 μm to about 40 μm.
19 . The semiconductor package as claimed in claim 14 , wherein:
a thickness of each of the upper substrate pads is less than a thickness of each of the wiring patterns,
the thickness of each of the upper substrate pads is in a range of about 1 μm to about 5 μm, and
the thickness of each of the wiring patterns is in a range of about 5 μm to about 20 μm.
20 . The semiconductor package as claimed in claim 14 , further comprising plating layers on the upper substrate pads, the plating layers being on only some of the upper substrate pads.