Semiconductor chip package having internal I/O structures with modulated thickness to compensate for die/substrate warpage
An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.
1 . An apparatus, comprising:
a substrate; and
I/O structures comprising pads and solder balls on the substrate to couple with a semiconductor chip, wherein a first subset of pads of the pads and solder balls in a first region of the substrate are thinner than a second subset of pads of the pads and solder balls in a second region of the substrate and wherein the substrate includes an embedded interconnect chip that is capable of interconnecting a first semiconductor chip on the substrate with a second semiconductor chip on the substrate.
2 . The apparatus of claim 1 wherein the first subset of pads are inner pads.
3 . The apparatus of claim 1 wherein the second subset of pads are outer pads of the pads and solder balls.
4 . The apparatus of claim 1 wherein the first subset of pads of the pads and solder balls and the second subset of pads of the pads and solder balls are electroplated metal.
5 . The apparatus of claim 1 wherein a first subset of balls of the pads and solder balls and a second subset of solder balls of the pads and solder balls are electroplated solder.
6 . The apparatus of claim 1 wherein the substrate is-any of:
a package substrate;
an interposer; or
a printed circuit board.
7 . The apparatus of claim 1 wherein a first subset of solder balls of the pads and solder balls is thinner than a second subset of solder balls of the pads and solder balls.
8 . The apparatus of claim 1 wherein the first subset of pads of the pads and solder balls and the second subset of pads of the pads and solder balls are located on the embedded interconnect chip.
9 . A system comprising:
a plurality of processing cores;
a memory;
a memory controller coupled between the plurality of processing cores and the memory;
a network interface; and
a second semiconductor chip, package comprising a first semiconductor chip and a semiconductor chip the semiconductor chip package comprising I/O structures, the I/O structures comprising pads and solder balls that are coupled to the first semiconductor chip, wherein a first subset of pads of the pads and solder balls are thinner than a second subset of pads of the pads and solder balls, wherein the semiconductor chip package also comprises a substrate, and wherein the substrate comprises an embedded interconnect chip that interconnects the first semiconductor chip with the second semiconductor chip.
10 . The system of claim 9 wherein the first subset of pads of the pads and solder balls are inner pads of the pads and solder balls.
11 . The system of claim 9 wherein the second subset of pads are outer pads of the pads and solder balls.
12 . The system of claim 9 wherein the first subset of pads of the pads and solder balls and the second subset of pads of the pads and solder balls are electroplated metal.
13 . The system of claim 9 wherein a first subset of solder balls of the pads and solder balls and a second subset of solder balls of the pads and solder balls are electroplated solder.
14 . The system of claim 9 wherein the substrate is:
a semiconductor chip package substrate or
an interposer.
15 . The system of claim 9 wherein a first subset of solder balls of the pads and solder balls is thinner than a second subset of solder balls of the pads and solder balls.
16 . The system of claim 9 wherein the first subset of pads of the pads and solder balls and the second subset of pads of the pads and solder balls are located on the embedded interconnect chip.