Integrated circuit package with improved heat dissipation efficiency and methods of forming the same
In an embodiment, a device includes a first integrated circuit die, wherein the first integrated circuit die includes a substrate formed of a semiconductor material and a conductive via penetrating through the substrate; a second integrated circuit die disposed laterally adjacent to the first integrated circuit die; a first gap-filling layer disposed between the first integrated circuit die and the second integrated circuit die, wherein the first gap-filling layer is formed of a material selected from silicon, silicon carbide, silicon oxynitride, silicon nitride, the semiconductor material of the substrate, or a combination thereof; and a third integrated circuit die attached to the first integrated circuit die in a face-to-back manner.
1 . A device comprising:
a first integrated circuit die, wherein the first integrated circuit die comprises a substrate formed of a semiconductor material and a conductive via penetrating through the substrate;
a second integrated circuit die disposed laterally adjacent to the first integrated circuit die;
a first gap-filling layer disposed between the first integrated circuit die and the second integrated circuit die, wherein the first gap-filling layer and the substrate of the first integrated circuit die comprise a same material and have different crystalline structures; and
a third integrated circuit die attached to the first integrated circuit die in a face-to-back manner.
2 . The device of claim 1 , further comprising a bonding film and a conductive bonding feature, wherein the conductive bonding feature is in the bonding film over the conductive via wherein the bonding film extends over the first integrated circuit die, the second integrated circuit die, and the first gap-filling layer and laterally surrounds a portion of the conductive via.
3 . The device of claim 2 , wherein the third integrated circuit die comprises a dielectric layer and a die connector in the dielectric layer, wherein the dielectric layer is bonded to the bonding film through a dielectric-to-dielectric bond, and the die connector is bonded to the conductive bonding feature through a metal-to-metal bond.
4 . The device of claim 1 , further comprising a second gap-filling layer disposed over the first gap-filling layer, wherein the second gap-filling layer is formed of a material selected from silicon, silicon carbide, silicon oxynitride, silicon nitride, the material of the first gap-filling layer, or a combination thereof.
5 . The device of claim 4 , wherein the second gap-filling layer extends over the second integrated circuit die and laterally surrounds the third integrated circuit die.
6 . The device of claim 4 , further comprising a through via penetrating through the second gap-filling layer, wherein the through via is electrically isolated from the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die.
7 . The device of claim 1 , further comprising a bonding film overlying the third integrated circuit die.
8 . The device of claim 7 , wherein the bonding film is a metal.
9 . The device of claim 1 , further comprising a second gap-filling film adjacent to the third integrated circuit die, and a conductive via extending through the second gap-filling film.
10 . A device comprising:
a first tier, comprising first integrated circuit dies and a first gap-filling layer disposed in a first gap between the first integrated circuit dies, wherein the first integrated circuit dies respectively comprise a substrate formed of a semiconductor material, wherein the first gap-filling layer is formed of a material having a thermal conductivity higher than 2 W/m·K and a coefficient of thermal expansion mismatch less than 1.3 μm/(m·K) with the semiconductor material;
a second tier disposed over the first tier, wherein the second tier comprises at least one second integrated circuit die and a second gap-filling layer disposed adjacent the at least one second integrated circuit die, wherein the at least one second integrated circuit die is bonded to one of the first integrated circuit dies in a face-to-back manner; and
a support substrate disposed over the at least one second integrated circuit die and the second gap-filling layer.
11 . The device of claim 10 , wherein the second gap-filling layer comprises a top surface level with a surface of the at least one second integrated circuit die, and on an opposite side of the second integrated circuit die relative to the first integrated circuit dies.
12 . The device of claim 11 , wherein the first gap-filling layer comprises a top surface higher than or lower than respective surfaces of the first integrated circuit dies, which are facing the at least one second integrated circuit die.
13 . The device of claim 10 , further comprising a through via penetrating the second gap-filling layer, wherein the through via is electrically isolated from the at least one second integrated circuit die.
14 . The device of claim 13 , further comprising a dielectric liner disposed between the second gap-filling layer, the at least one second integrated circuit die, and the first gap-filling layer, wherein the through via penetrates through the dielectric liner.
15 . The device of claim 13 , further comprising a metal film disposed between the support substrate and the at least one second integrated circuit die and between the support substrate and the second gap-filling layer, wherein the through via is in physical contact with the metal film.
16 . A method comprising:
disposing a first integrated circuit die and a second integrated circuit die over a carrier substrate, wherein the first integrated circuit die comprises a substrate formed of a semiconductor material;
forming a first gap-filling layer in a gap between the first integrated circuit die and the second integrated circuit die, wherein the first gap-filling layer comprises the semiconductor material of the substrate;
attaching a third integrated circuit die to the first integrated circuit die in a face-to-back manner;
forming a second gap-filling layer over the first gap-filling layer and laterally adjacent to the third integrated circuit die; and
forming a through via penetrating through the second gap-filling layer.
17 . The method of claim 16 , wherein the first integrated circuit die comprises a conductive via in the substrate when being disposed over the carrier substrate, wherein the method further comprises performing a recessing process to recess the substrate and expose the conductive via before attaching the third integrated circuit die to the first integrated circuit die.
18 . The method of claim 17 , wherein the recessing process comprises recessing the first gap-filling layer.
19 . The method of claim 18 , further comprising forming a bonding film laterally around a portion of the conductive via and over the first gap-filling layer, wherein the third integrated circuit die comprises a dielectric layer bonded to the bonding film through dielectric-to-dielectric bonds.