Semiconductor package

1 . A semiconductor package, comprising:

a first semiconductor structure comprising a first semiconductor substrate and a lower through structure that penetrates the first semiconductor substrate;

a connection structure on the first semiconductor structure; and

a second semiconductor structure on the connection structure, the second semiconductor structure comprising a second semiconductor substrate and an upper through structure that penetrates the second semiconductor substrate,

wherein the connection structure comprises:

a lower curved pad on the lower through structure; and

an upper curved pad on the lower curved pad,

wherein a top surface of the lower curved pad comprises a curved surface,

wherein a bottom surface of the upper curved pad comprises a curved surface, and

wherein the upper curved pad is connected to the upper through structure.

2 . The semiconductor package of claim 1 , wherein the connection structure further comprises:

a plurality of upper conductive pads contacting the upper through structure; and

a first top pad on the upper curved pad, and

wherein a width of the plurality of upper conductive pads is less than a width of the first top pad.

3 . The semiconductor package of claim 1 , wherein the connection structure further comprises:

an upper connection pad spaced apart from the upper curved pad;

a first top pad on the upper curved pad; and

a connection topmost pad on the upper connection pad, and

wherein a width of the connection topmost pad is greater than a width of the first top pad.

4 . The semiconductor package of claim 1 , wherein the connection structure further comprises:

a lower dielectric layer on the first semiconductor substrate; and

a lower connection pad spaced apart from the lower curved pad,

wherein an entirety of a bottom surface of the lower connection pad contacts the lower dielectric layer, and

wherein a bottom surface of the lower curved pad contacts the lower through structure.

5 . The semiconductor package of claim 4 , wherein the top surface of the lower curved pad is at a level that is lower than a level of a top surface of the lower connection pad.

6 . The semiconductor package of claim 1 , wherein the connection structure further comprises:

a lower dielectric layer on the first semiconductor substrate; and

an intervening layer on the lower dielectric layer, and

wherein a top surface of the intervening layer is at a level that is lower than a level of the top surface of the lower curved pad.

7 . The semiconductor package of claim 1 , wherein the connection structure further comprises a first top pad on the upper curved pad, and

wherein the first top pad comprises a material that is different from a material of the upper curved pad.

8 . The semiconductor package of claim 7 , wherein the top surface of the lower curved pad has a curvature that is substantially the same as a curvature of the bottom surface of the upper curved pad.

9 . The semiconductor package of claim 1 , wherein the connection structure further comprises:

an upper connection pad spaced apart from the upper curved pad;

a first top pad on the upper curved pad; and

a connection topmost pad on the upper connection pad, and

wherein a top surface of the connection topmost pad is at a level that is higher than a level of a top surface of the first top pad.

10 . The semiconductor package of claim 9 , wherein the connection structure further comprises a bonding dielectric layer below the second semiconductor substrate,

wherein an entirety of the top surface of the connection topmost pad contacts the bonding dielectric layer, and

wherein the top surface of the first top pad contacts the upper through structure.

11 . A semiconductor package, comprising:

a first semiconductor structure comprising a first semiconductor substrate and a lower through structure that penetrates the first semiconductor substrate;

a connection structure on the first semiconductor structure; and

a second semiconductor structure on the connection structure, the second semiconductor structure comprising a second semiconductor substrate and an upper through structure that penetrates the second semiconductor substrate,

wherein the connection structure comprises:

a lower dielectric layer on the first semiconductor substrate;

at least one lower curved pad on the lower dielectric layer and connected to the lower through structure; and

at least one lower connection pad on the lower dielectric layer and spaced apart from the at least one lower curved pad, and

wherein a top surface of the at least one lower curved pad is at a level that is lower than a level of a top surface of the at least one lower connection pad.

12 . The semiconductor package of claim 11 , wherein the connection structure further comprises an upper curved pad on the at least one lower curved pad,

wherein the top surface of the at least one lower curved pad comprises a curved surface,

wherein a bottom surface of the upper curved pad comprises a curved surface, and

wherein the top surface of the at least one lower connection pad comprises a flat surface.

13 . The semiconductor package of claim 12 , wherein the bottom surface of the upper curved pad has a curvature that is substantially the same as a curvature of the top surface of the at least one lower curved pad.

14 . The semiconductor package of claim 11 , wherein a width of the at least one lower curved pad is less than a width of the at least one lower connection pad.

15 . The semiconductor package of claim 11 , wherein the connection structure further comprises:

an upper connection pad on the at least one lower connection pad; and

a connection topmost pad on the upper connection pad,

wherein the lower through structure at least partially overlaps the at least one lower connection pad, and

wherein the at least one lower connection pad at least partially overlaps the connection topmost pad.

16 . The semiconductor package of claim 11 , wherein the connection structure further comprises:

an upper connection pad on the at least one lower connection pad; and

a connection topmost pad on the upper connection pad, and

wherein a width of the connection topmost pad is greater than a width of the upper connection pad.

17 . The semiconductor package of claim 11 , wherein the connection structure further comprises:

an upper connection pad on the at least one lower connection pad; and

a bonding dielectric layer below the second semiconductor substrate,

wherein the at least one lower connection pad contacts the upper connection pad, and

wherein an entirety of the top surface of the at least one lower curved pad contacts the bonding dielectric layer.

18 . The semiconductor package of claim 11 , further comprising:

a plurality of lower connection pads, the at least one lower connection pad being among the plurality of lower connection pads, and

a plurality of lower curved pads, the at least one lower curved pad being among the plurality of lower curved pads,

wherein the plurality of lower curved pads are respectively between the plurality of lower connection pads.

19 . A semiconductor package, comprising:

a first semiconductor structure comprising a first semiconductor substrate and a lower through structure that penetrates the first semiconductor substrate;

a connection structure on the first semiconductor structure; and

a second semiconductor structure on the connection structure, the second semiconductor structure comprising a second semiconductor substrate and an upper through structure that penetrates the second semiconductor substrate,

wherein the connection structure comprises:

a lower dielectric layer on the first semiconductor substrate;

an intervening layer on the lower dielectric layer;

a lower curved pad on the lower through structure; and

an upper curved pad on the lower curved pad,

wherein a top surface of the lower curved pad comprises a curved surface,

wherein a bottom surface of the upper curved pad comprises a curved surface,

wherein the upper curved pad is connected to the upper through structure, and

wherein a top surface of the intervening layer is at a level that is lower than a level of the top surface of the lower curved pad.

20 . The semiconductor package of claim 19 , wherein the intervening layer comprises silicon nitride, and

wherein the lower dielectric layer comprises silicon oxide.