Three dimensional heterogeneous integration with double-sided semiconductor dies and methods of forming the same

1 . A semiconductor package structure, comprising:

an interposer;

a first semiconductor die stack electrically connected to the interposer and comprising:

a first semiconductor die comprising a first front-side interconnect structure and a first back-side interconnect structure, and

a second semiconductor die comprising a second front-side interconnect structure and a second back-side interconnect structure, wherein the first back-side interconnect structure is electrically connected to the second front-side interconnect structure; and

a second semiconductor die stack electrically connected to the interposer,

wherein the first semiconductor die is a first singulated semiconductor die including a first central portion disposed between first front-side interconnect structure and the second back-side interconnect structure; and

wherein the first central portion comprises:

first field effect transistors laterally spaced by first shallow trench isolation structures,

a first planarization dielectric layer overlying or underlying the first shallow trench isolation structures and laterally surrounding the first field effect transistors, and

first conductive vias which are located outside of, and laterally spaced from, the first field effect transistors, vertically extend through the first shallow trench isolation structures and the first planarization dielectric layer, contact a respective front-side electrical interconnect in the first front-side interconnect structure in a horizontal plane containing a planar surface of the planarization dielectric layer, and contacts a respective back-side electrical interconnect in the first back-side interconnect structure.

2 . The semiconductor package structure of claim 1 , wherein:

the first semiconductor die comprises a first central portion disposed between the first front-side interconnect structure and the first back-side interconnect structure;

the second semiconductor die comprises a second central portion disposed between the second front-side interconnect structure and the second back-side interconnect structure; and

each of the first central portion and the second central portion comprises electrical circuit elements formed in or on a semiconductor substrate.

3 . The semiconductor package structure of claim 1 , wherein each of the first front-side interconnect structure, the first back-side interconnect structure, the second front-side interconnect structure, and the second back-side interconnect structure comprises electrical interconnects formed within a dielectric layer.

4 . The semiconductor package structure of claim 2 , wherein:

the first central portion comprises first vias that electrically connect the first front-side interconnect structure to the first back-side interconnect structure; and

the second central portion comprises second vias that electrically connect the second front-side interconnect structure to the second back-side interconnect structure.

5 . The semiconductor package structure of claim 4 , wherein:

the first vias are formed within first shallow trench isolation structures between first transistor structures formed in the first central portion; and

the second vias are formed within second shallow trench isolation structures between second transistor structures formed in the second central portion.

6 . The semiconductor package structure of claim 5 , wherein each of the first vias and the second vias comprise a width that is in a range from 10 nm to 20 nm.

7 . The semiconductor package structure of claim 1 , wherein the first back-side interconnect structure is electrically connected to the second front-side interconnect structure with hybrid bonding structures in which first electrical bonding structures of the first back-side interconnect structure are bonded to second electrical bonding structures of the second front-side interconnect structure with direct metal-to-metal bonds.

8 . The semiconductor package structure of claim 7 , wherein the first back-side interconnect structure is formed in a first dielectric layer and the second front-side interconnect structure is formed in a second dielectric layer, and wherein the hybrid bonding structures further comprise direct dielectric-to-dielectric bonds between the first dielectric layer and the second dielectric layer.

9 . The semiconductor package structure of claim 7 , wherein the first electrical bonding structures and the second electrical bonding structures are configured as a periodic array having a pitch that is in a range from 0.1 microns to 10 microns.

10 . The semiconductor package structure of claim 1 , wherein each of the first front-side interconnect structure and the second front-side interconnect structure comprises 10 to 20 interconnect levels formed in 10 to 20 respective front-side dielectric layers, and wherein each of the first back-side interconnect structure and the second back-side interconnect structure comprises 5 to 10 interconnect levels formed in 5 to 10 respective back-side dielectric layers.

11 . The semiconductor package structure of claim 1 , further comprising:

a third semiconductor die comprising a third front-side interconnect structure and a third back-side interconnect structure,

wherein the second back-side interconnect structure of the second semiconductor die is electrically connected to the third front-side interconnect structure of the third semiconductor die.

12 . The semiconductor package structure of claim 11 , wherein:

the first semiconductor die comprises first logic circuits;

the second semiconductor die comprises first memory circuits; and

the third semiconductor die comprises one of second logic circuits, second memory circuits, image processing circuits, power delivery circuits, analog circuits, passive device components, and thermal dispersion components.

13 . The semiconductor package structure of claim 12 , wherein at least one of the first semiconductor die, the second semiconductor die, and the third semiconductor die corresponds to a different technology node than another of the first semiconductor die, the second semiconductor die, and the third semiconductor die.

14 . A semiconductor package structure, comprising:

an interposer;

a first die stack electrically connected to the interposer; and

a second die stack electrically connected to the interposer,

wherein the first die stack and the second die stack each comprise two or more semiconductor dies stacked such that a back-side interconnect structure of one semiconductor die is electrically connected to a front-side interconnect structure of another semiconductor die,

wherein the semiconductor dies in the first die stack and the second die stack are singulated semiconductor dies including a respective central portion disposed between a respective front-side interconnect structure and a respective back-side interconnect structure; and

wherein the respective central portion comprises:

respective field effect transistors laterally spaced by respective shallow trench isolation structures,

a respective planarization dielectric layer overlying or underlying the respective shallow trench isolation structures and laterally surrounding the respective field effect transistors, and

respective conductive vias which are located outside of, and laterally spaced from, the respective field effect transistors, vertically extend through the respective shallow trench isolation structures and the respective planarization dielectric layer, contact a respective front-side electrical interconnect in the respective front-side interconnect structure in a horizontal plane containing a planar surface of the planarization dielectric layer, and contacts a respective back-side electrical interconnect in the respective back-side interconnect structure.

15 . The semiconductor package structure of claim 14 , wherein:

the first die stack further comprises:

a first semiconductor die comprising a first front-side interconnect structure and a first back-side interconnect structure; and

a second semiconductor die comprising a second front-side interconnect structure and a second back-side interconnect structure,

wherein the first back-side interconnect structure is electrically connected to the second front-side interconnect structure, and

the second die stack further comprises:

a third semiconductor die comprising a third front-side interconnect structure and a third back-side interconnect structure; and

a fourth semiconductor die comprising a fourth front-side interconnect structure and a fourth back-side interconnect structure,

wherein the third back-side interconnect structure is electrically connected to the fourth front-side interconnect structure.

16 . The semiconductor package structure of claim 14 , wherein each of the two or more semiconductor dies comprise a central portion disposed between a front-side interconnect structure and a back-side interconnect structure, and

wherein the central portion comprises electrical circuit elements formed in or on a semiconductor substrate.

17 . The semiconductor package structure of claim 16 , wherein each of the front-side interconnect structure and the back-side interconnect structure comprise electrical interconnects formed within a dielectric layer, and

wherein the central portion further comprises vias that electrically connect the front-side interconnect structure to the back-side interconnect structure.

18 . A semiconductor package structure, comprising:

an interposer;

a first die stack electrically connected to the interposer; and

a second die stack electrically connected to the interposer,

wherein each of the first die stack and the second die stack comprises double-sided semiconductor dies vertically stacked such that a back-side interconnect structure of one semiconductor die is directly bonded to a front-side interconnect structure of an adjacent semiconductor die via hybrid bonding structures including direct metal-to-metal bonds between electrical bonding structures and direct dielectric-to-dielectric bonds between dielectric layers, the hybrid bonding structures arranged in a periodic array across interfacing surfaces of the back-side interconnect structure and the front-side interconnect structure;

wherein each double-sided semiconductor die comprises a vertical stack including a front-side interconnect structure, a central portion, and a back-side interconnect structure; and

wherein the central portion comprises:

a semiconductor substrate portion having a front surface and a back surface,

field effect transistors located on the front surface of the semiconductor substrate portion as front-end-of-line electrical circuit elements with gate structures, source regions, and drain regions, the field effect transistors laterally spaced by shallow trench isolation structures embedded within the semiconductor substrate portion,

a planarization dielectric layer overlying or underlying the first shallow trench isolation structures and laterally surrounding the first field effect transistors, and

conductive vias located outside of, and laterally spaced from, the field effect transistors and vertically extending through the shallow trench isolation structures to electrically connect the front-side interconnect structure to the back-side interconnect structure while being laterally positioned between adjacent field effect transistors and contacting a respective front-side electrical interconnect in the front-side interconnect structure in a horizontal plane containing a planar surface of the planarization dielectric layer and contacting a respective back-side electrical interconnect in the back-side interconnect structure.

19 . The semiconductor package structure of claim 18 , wherein:

the hybrid bonding structures provide direct contact between the electrical bonding structures of the back-side interconnect structure of an underlying semiconductor die and the electrical bonding structures of the front-side interconnect structure of an overlying semiconductor die, and direct contact between the dielectric layers of the back-side interconnect structure of the underlying semiconductor die and the dielectric layers of the front-side interconnect structure of the overlying semiconductor die;

the interfacing surfaces are in continuous physical engagement without intervening bonding materials; and

the conductive vias within the shallow trench isolation structures of the central portion maintaining electrical continuity across the vertical stack of the double-sided semiconductor die while being isolated from the gate structures, source regions, and drain regions of the field effect transistors on the front surface of the semiconductor substrate portion.

20 . The semiconductor package structure of claim 19 , wherein:

the direct metal-to-metal bonds and the direct dielectric-to-dielectric bonds form a seamless interface geometry between the underlying semiconductor die and the overlying semiconductor die;

the conductive vias are laterally embedded within the shallow trench isolation structures to isolate the field effect transistors formed on the front surface of the semiconductor substrate portion; and

the central portion provides electrical connections through the semiconductor substrate portion from the front surface to the back surface without penetrating through active regions of the field effect transistors including the gate structures, source regions, and drain regions.