Dynamic low and high-frequency device characterization
Examples provide internally reconfigurable bias tees for a vector network analyzer. The bias tees can have component sizes that can be electronically switched during device testing. To reduce test time when multiple tests are conducted, examples can further provide for automatic tuning of one or more components of a bias tee, where the one or more components are tuned for the test being performed.
1 . A test system comprising:
a vector network analyzer having a first number of test ports;
a second number of bias tees, each of the second number of bias tees coupled to a different one of the first number of test ports, wherein at least one of the second number of bias tees comprises a variable component, and wherein the second number is less than or equal to the first number; and
a DC parameter analyzer having a first port to provide a first bias output, wherein the first number of test ports of the vector network analyzer includes a first test port to provide an input radio-frequency (RF) signal, wherein the second number of bias tees includes a first bias tee to receive the input RF signal and the first bias output, and wherein the first bias tee comprises a first variable component.
2 . The test system of claim 1 wherein the vector network analyzer further comprises a second test port to receive an output RF signal, the DC parameter analyzer comprises a second port to provide a second bias output, and the test system further comprises a second bias tee to provide the output RF signal and the second bias output, wherein the second bias tee comprises a second variable component.
3 . The test system of claim 2 wherein the vector network analyzer further comprises a control circuit having a first control line output to provide a first control signal, where the first control signal adjusts the first variable component, and a second control line output to provide a second control signal, where the second control signal adjusts the second variable component.
4 . The test system of claim 2 wherein the DC parameter analyzer further comprises a first control line output to provide a first control signal, where the first control signal adjusts the first variable component, and a second control line output to provide a second control signal, where the second control signal adjusts the second variable component.
5 . The test system of claim 2 wherein the first bias tee and the second bias tee are included in the vector network analyzer.
6 . The test system of claim 2 wherein the first bias tee is isolated from a measurement circuit of the vector network analyzer by a first RF coupler and the second bias tee is isolated from the measurement circuit of the vector network analyzer by a second RF coupler.
7 . The test system of claim 2 wherein the first bias tee and the second bias tee are included in the DC parameter analyzer.
8 . The test system of claim 2 wherein the first bias tee, the second bias tee and the DC parameter analyzer are included in the vector network analyzer.
9 . The test system of claim 2 wherein the first variable component is an inductor formed by a first series of inductors that are switchable using a first plurality of switches and the second variable component is an inductor formed by a second series of inductors that are switchable using a second plurality of switches.
10 . The test system of claim 9 wherein the first variable component further comprises a first plurality of damping components coupled to inductors in the first series of inductors and the second variable component further comprises a second plurality of damping components coupled to inductors in the second series of inductors.
11 . A vector network analyzer comprising:
a first number of test ports;
a second number of bias tees, each of the second number of bias tees coupled to a different one of the first number of test ports, wherein at least one of the second number of bias tees comprises a variable component, and wherein at least one of the second number of bias tees are housed in the vector network analyzer, and wherein the second number is less than or equal to the first number;
a first radio frequency (RF) source to provide a first RF signal;
a first bias tee in the second number of bias tees to receive the first RF signal, wherein the first bias tee comprises a first variable component, wherein the first bias tee provides a second RF signal, and wherein the first bias tee is housed in the vector network analyzer;
a first test port in the first number of test ports to provide the second RF signal to a device-under-test, the device-under-test external to the vector network analyzer;
a second test port in the first number of test ports to receive a third RF signal from the device; and
a second bias tee in the second number of bias tees to receive the third RF signal, wherein the second bias tee comprises a second variable component, and wherein the second bias tee is housed in the vector network analyzer.
12 . The vector network analyzer of claim 11 wherein the first bias tee and the second bias tee are not user replaceable components.
13 . The vector network analyzer of claim 12 wherein the first bias tee and the second bias tee are fixed in place in the vector network analyzer and are not intended to be removed.
14 . The vector network analyzer of claim 12 wherein the first RF signal is received by a first capacitor of the first bias tee and a bias voltage is received by the first variable component, where the first variable component is an inductor component.
15 . The vector network analyzer of claim 14 wherein the inductor component comprises a first switch coupled to a first inductor.
16 . The vector network analyzer of claim 15 wherein the vector network analyzer further comprises a control circuit having a control line output coupled to a gate of the first switch.
17 . A computer-readable storage medium having stored therein program code instructions that, when executed by a processor in the vector network analyzer of claim 1 , cause the processor to perform a method comprising:
determine a test to be performed on a device;
based on the test, determine a first configuration for a first component of a first bias tee in the second number of bias tees;
based on the test, determine a second configuration for a second component of a second bias tee in the second number of bias tees;
send a first signal to configure the first component in the first configuration; and
send a second signal to configure the second component in the second configuration.
18 . The computer-readable storage medium of claim 17 wherein the first component is a first variable inductor comprising a first plurality of individual inductors and the second component is a second variable inductor comprising a second plurality of individual inductors.
19 . The computer-readable storage medium of claim 18 wherein the first signal drives a gate of a first switch having a drain coupled to a first inductor in the first plurality of individual inductors and the second signal drives a gate of a second switch having a drain coupled to a first inductor in the second plurality of individual inductors.
20 . The computer-readable storage medium of claim 17 wherein the computer-readable storage medium is a memory in the vector network analyzer.