Synchronous power state control scheme for multi-chip integrated power management solution in embedded systems
Methods and apparatus for power management of embedded devices are provided. An example apparatus includes a primary power management integrated circuit (PMIC) to communicate with an embedded system to determine a power state. The example primary PMIC is to include a first power state sequence controller and a first power supply controller. The example first power state sequence controller is to drive a first power supply controller according to the power state. The example first power supply controller is to activate a first set of rails to apply power to the embedded system. The example apparatus includes a secondary PMIC including a second power state sequence controller and a second power supply controller. The example second power sequence controller is to drive a second power supply controller according to the power state. The example second power supply controller is to activate a second set of rails to apply power to the embedded system.
1 . A method comprising:
receiving, by a first power management circuit, an enable signal;
querying, by the first power management circuit, an embedded system for power state information indicating a requested power state of the embedded system in response to the receiving the enable signal;
receiving, by the first power management circuit, from the embedded system, a power state control signal indicating the requested power state in response to the querying the embedded system for the power state information;
determining, by the first power management circuit, a first power state for the first power management circuit and a second power state for a second power management circuit based on the power state control signal indicating the requested power state;
transmitting, by the first power management circuit, to the second power management circuit, a signal indicating the second power state;
transitioning, by the first power management circuit, to the first power state to generate a first output power for the embedded system; and
transitioning, by the second power management circuit, to the second power state to generate a second output power for the embedded system based on the signal in synchrony with the transitioning, by the first power management circuit, to the first power state.
2 . The method of claim 1 , wherein:
the first power management circuit includes signal arbitration logic that processes the power state control signal.
3 . The method of claim 2 , wherein:
the power state control signal includes multiple activation signals; and
the first power management circuit arbitrates among the multiple activation signals to determine a priority for the multiple activation signals.
4 . The method of claim 1 , further comprising:
determining, by the first power management circuit, an error based on a difference between the first output power and an effective power output.
5 . The method of claim 1 , wherein:
the first power management circuit includes a communication interface.
6 . The method of claim 5 , wherein:
the communication interface is coupled with the second power management circuit.
7 . The method of claim 6 , wherein:
the communication interface determines a communication error with the second power management circuit.
8 . The method of claim 6 , further comprising:
transmitting, by the first power management circuit, to the second power management circuit, the signal indicating the second power state via the communication interface.
9 . A system, comprising:
a system on a chip (SOC);
a first power supply circuit configured to query the SOC for power state information indicating a requested power state of a set of discrete power states of the SOC; and
a second power supply circuit coupled to the first power supply circuit,
wherein:
the SOC is configured to:
provide a power state control signal indicating the requested power state to the first power supply circuit in response to the query;
the first power supply circuit is configured to:
receive the power state control signal indicating the requested power state;
determine a first power state for the first power supply circuit and a second power state for the second power supply circuit based on the power state control signal;
provide a first signal associated with the second power state to the second power supply circuit; and
transition to the first power state to generate a first output voltage for the SOC;
the second power supply circuit is configured to:
receive the first signal; and
transition to the second power state to generate a second output voltage for the SOC based on the received first signal in synchrony with the transition to the first power state by the first power supply circuit.
10 . The system of claim 9 , wherein:
the first power supply circuit is further configured to:
determine a third power state for the second power supply circuit, wherein the third power state corresponds to a third output voltage from the second power supply circuit; and
provide a second signal associated with the third power state to the second power supply circuit; and
the second power supply circuit is configured to:
receive the second signal; and
transition from the second power state to the third power state based on the received second signal to generate the third output voltage for the SOC.
11 . The system of claim 9 , wherein the set of discrete power states includes one or more of: an active state, a sleep state, a standby state, a safe state, or an off state.
12 . The system of claim 9 , further comprising:
an interface configured to couple the first power supply circuit and the second power supply circuit,
wherein the first power supply circuit is configured to provide the first signal to the second power supply circuit through the interface.
13 . The system of claim 12 , wherein the first power supply circuit is further configured to provide a clock signal to the second power supply circuit through the interface.
14 . The system of claim 9 , wherein:
the second power supply circuit is configured to:
determine an error associated with the second power supply circuit; and
provide a fourth signal associated with the error to the first power supply circuit; and
the first power supply circuit is configured to:
provide a fifth signal to the SOC indicating the error associated with the second power supply circuit based on the fourth signal.
15 . The system of claim 9 , wherein the SOC includes a processor.
16 . The system of claim 9 , wherein the first power supply circuit is configured to provide the first output voltage to a first voltage rail of the SOC, and wherein the second power supply circuit is configured to provide the second output voltage to a second voltage rail of the SOC.
17 . The system of claim 9 , wherein the first power supply circuit is configured to:
receive an enable signal; and
transition to an initial power state to generate an initial voltage for the SOC in response to receiving the enable signal; and
query the SOC for the power state information in response to the transition to the initial power state.
18 . The system of claim 9 , wherein the second power supply circuit is configured to provide, to the first power supply circuit, feedback indicating a status of the transition to the second power state, and wherein the first power supply circuit is configured to provide, to the SOC, feedback indicating a status of the transition to the first power state and the status of the transition to the second power state.
19 . An apparatus comprising:
a first power management circuit and a second power management circuit coupled to the first power management circuit, the first power management circuit configured to:
receive an enable signal;
transition to an initial power state to provide an initial output power to an embedded system in response to receiving the enable signal;
query the embedded system for power state information indicating a requested power state of a set of discrete power states in response to transitioning to the initial power state;
receive a power state control signal indicating the requested power state from the embedded system in response to querying the embedded system for the power state information;
determine both a first power state for the first power management circuit and a second power state for the second power management circuit based on the power state control signal indicating the requested power state;
transmit a signal indicating the second power state to the second power management circuit in response to determining both the first power state and the second power state based on the power state control signal; and
transition to the first power state to provide a first output power to the embedded system in response to transmitting the signal indicating the second power state to the second power management circuit; and
the second power management circuit configured to:
transition to the second power state to provide a second output power to the embedded system substantially simultaneously with the transition to the first power state by the first power management circuit.
20 . The apparatus of claim 19 , wherein the second power management circuit is configured to transmit, to the first power management circuit, feedback indicating a status of the transition to the second power state by the second power management circuit, and wherein the first power management circuit is configured to transmit, to the embedded system, feedback indicating a status of the transition to the first power state by the first power management circuit and indicating the status of the transition to the second power state by the second power management circuit.