Storage device, computing system and proximity data processing module with improved efficiency of memory bandwidth
A method is provided in which a core processor located adjacent to a memory and processing data of the memory in a proximity data processing scheme reads and processes the data of the memory by simultaneously using a plurality of channels used by the memory. Since data processing is performed simultaneously using a total bandwidth between the memory and the core processor, the efficiency of the proximity data processing scheme by the core processor may be improved.
1 . A storage device comprising:
a memory including a plurality of memory cells;
a core processor located adjacent to the plurality of memory cells, and configured to access the memory using an N (where N is an integer equal to or greater than 2) number of channels and to process data of the memory; and
an internal splitter configured to simultaneously read data through at least two channels from among the N number of channels, to merge the simultaneously read data, and to provide the merged data to the core processor, and
wherein the internal splitter converts logical addresses to physical addresses, the physical addresses are allocated sequentially for each of the N number of channels, and the logical addresses are allocated in a different direction from the physical addresses, and are allocated sequentially for all of the N number of channels, and
wherein each of the read data in the N number of channels has a physical address corresponding to a logical address.
2 . The storage device according to claim 1 , wherein the internal splitter provides physical addresses that are mapped to logical addresses sequentially allocated to the N number of channels and that are sequentially allocated to the N number of respective channels.
3 . The storage device according to claim 1 , wherein the data is split into units of a data bus width of each of the number of channels and is loaded into the memory through the N number of channels.
4 . The storage device according to claim 1 , wherein, when the data is loaded into the memory, physical addresses that are allocated in a first direction for each of the N number of channels are converted into logical addresses that are allocated in a second direction different from the first direction.
5 . The storage device according to claim 1 , wherein at least two data simultaneously loaded through at least two channels from among the N number of channels configure a command.
6 . The storage device according to claim 1 , wherein at least two data loaded through any one channel from among the N number of channels configure a part of a command.
7 . The storage device according to claim 1 , wherein
a first data simultaneously loaded through a first channel from among the N number of channels and a second data simultaneously loaded through a second channel configure a part of a command, and
at least one of the first data or the second data is larger than a data bus width of each of the N number of channels.
8 . The storage device according to claim 7 , wherein a size of the first data is different from a size of the second data.
9 . The storage device according to claim 1 , wherein, when a command is loaded into the memory, the number of times the N number of channels are accessed is equal to or less than N.
10 . The storage device according to claim 1 , wherein the core processor is located outside the memory.
11 . The storage device according to claim 1 , wherein the core processor is located inside the memory.
12 . The storage device according to claim 1 , wherein the core processor is separate from a host which is located outside the memory.
13 . A computing system comprising:
a memory using N (where N is an integer equal to or greater than 2) number of channels;
a first splitter configured to, when data is loaded into the memory, convert physical addresses, which are allocated sequentially for each of the N number of channels, into logical addresses that are allocated in a different direction from the physical addresses and are allocated sequentially for all of the N number of channels; and
a second splitter configured to, when the data loaded into the memory is read, provide physical addresses mapped to the logical addresses,
wherein each of the read data in the N number of channels has a physical address corresponding to a logical address.
14 . The computing system according to claim 13 , wherein the second splitter provides the physical addresses mapped to the logical addresses to at least two channels, respectively, from among the N number of channels.
15 . The computing system according to claim 13 , wherein the data is simultaneously loaded into at least two of the N number of channels by the first splitter, and the data is simultaneously read from at least two of the N number of channels by the second splitter.
16 . The computing system according to claim 13 , wherein the second splitter is located inside the memory or adjacent to the memory, and the first splitter is located outside the memory.
17 . The computing system according to claim 13 , wherein the first splitter and the second splitter are located inside the memory or adjacent to the memory.
18 . A proximity data processing module comprising:
an internal splitter configured to provide physical addresses mapped to logical addresses for each of a plurality of channels used by a memory; and
a core processor configured to read data of the memory simultaneously using the plurality of channels according to the physical addresses, and to perform a calculation according to the data, and
wherein the internal splitter converts the logical addresses to the physical addresses, the physical addresses are allocated sequentially for each of an N number of channels, and the logical addresses are allocated in a different direction from the physical addresses, and are allocated sequentially for all of the N number of channels, and
wherein each of the read data in the N number of channels has a physical address corresponding to a logical address.
19 . The proximity data processing module according to claim 18 , wherein the physical addresses are sequentially allocated to the plurality of respective channels.
20 . The proximity data processing module according to claim 18 , wherein the logical addresses, generated as the physical addresses that are allocated in a first direction, are converted to be allocated in a second direction different from the first direction.