Memory controller, control method for memory controller, and storage medium
A memory controller that issues a command to access a plurality of memories sharing a data signal, the memory controller comprising: a holding circuit configured to hold a read and/or write access request; and a control circuit configured to select an arbitrary access request from the access requests held in the holding circuit and to issue a read command and/or a write command, wherein the control circuit controls not to select, for a predetermined period from issuance of a read command and/or a write command immediately preceding, an access request to a memory other than a memory to which the read command and/or the write command was issued immediately preceding, from among the access requests held in the holding circuit.
1 . A memory controller that issues a command to access a plurality of memory devices including a first memory device and a second memory device which is different from the first memory device, wherein the first memory device comprises a plurality of first banks and the second memory device comprises a plurality of second banks which are different from the plurality of first banks, the memory controller comprising: a holding circuit configured to hold a read and/or write access request which comprises a target memory device and a target bank; and a control circuit configured to select an access request from the access requests held in the holding circuit and to issue a read command and/or a write command based on the selected access request, wherein the control circuit controls, in a case where a first access request to the first memory device is selected and then a first read command and/or write command is issued, to prohibit to select a second access request to the second memory for a predetermined period after elapse of a tCCD period (Column to Column Delay period) of the first read command and/or write command, wherein the predetermined period after elapse of a tCCD period is greater than the tCCD period, and the control circuit controls, in a case where the first access request to the first memory device is selected and then the first read command and/or write command is issued, to permit to select a third access request to the first memory for the predetermined period.
2 . The memory controller according to claim 1 , wherein, in a case where a read command is issued immediately preceding, the period is a period during which a read command cannot be issued to the second memory device.
3 . The memory controller according to claim 1 , wherein, in a case where a write command is issued immediately preceding, the period is a period during which a write command cannot be issued to the second memory device.
4 . The memory controller according to claim 1 , wherein the control circuit selects the access request based on a priority access type indicating which of the read command and the write command is to be preferentially issued.
5 . The memory controller according to claim 1 , further comprising a first determination circuit configured to determine whether or not, for each of the memory access requests stored in the holding circuit, a target page is open in a target bank of a target memory, and to output the memory access request that is for the target page being open.
6 . The memory controller according to claim 5 , further comprising a second determination circuit configured to output, among the memory access requests output by the first determination circuit, a memory access request corresponding to a priority access type indicating whether it is a period for preferentially issuing the read command or a period for preferentially issuing the write command.
7 . The memory controller according to claim 6 , further comprising a third determination circuit configured to output, among the memory access requests output by the second determination circuit, a memory access request for which waiting for command issuance due to memory switching does not occur.
8 . The memory controller according to claim 7 , further comprising a request selection circuit configured to select a memory access request from the memory access requests output by the third determination circuit, and to generate and output the read command or the write command of the memory access request being selected.
9 . The memory controller according to claim 1 , wherein the control circuit is configured to be able to select, after elapse of the period, an access request to the second memory device.
10 . The memory controller according to claim 1 , further comprising a timer configured to set a period after issuance of the read command, during which the read command cannot be issued to a different memory, and to start decrementing.
11 . The memory controller according to claim 1 , further comprising a timer configured to set a period after issuance of the write command, during which the write command cannot be issued to a different memory, and to start decrementing.
12 . The memory controller according to claim 1 , further comprising:
a timer configured to start decrementing from issuance of the first read command and/or write command; and
wherein the control circuit controls not to select, if the timer indicates one or more, the second access request to the second memory device, and
the control circuit controls to be able to select, after the timer indicates zero, the second access request to the second memory device, and to issue the second read command and/or write command in a case where the second access request is selected.
13 . A control method for a memory controller that issues a command to access a plurality of memory devices including a first memory device and a second memory device which is different from the first memory device, wherein the first memory device comprises a plurality of first banks and the second memory device comprises a plurality of second banks which are different from the plurality of first banks, the memory controller including a holding circuit configured to hold a read and/or write access request which comprises a target memory device and a target bank, and a control circuit configured to select an access request from the access requests held in the holding circuit and to issue a read command and/or a write command based on the selected access request, and the control method comprising: controlling, in a case where a first access request to the first memory device is selected and then a first read command and/or write command is issued, to prohibit to select a second access request to the second memory for a predetermined period after elapse of a tCCD period (Column to Column Delay period) of the first read command and/or write command, wherein the predetermined period after elapse of a tCCD period is greater than the tCCD period, and controlling, in a case where the first access request to the first memory device is selected and then the first read command and/or write command is issued, to permit to select a third access request to the first memory for the predetermined period.
14 . A non-transitory computer-readable storage medium storing a program to cause a computer to execute a control method for a memory controller that issues a command to access a plurality of memory devices including a first memory device and a second memory device which is different from the first memory device, wherein the first memory device comprises a plurality of first banks and the second memory device comprises a plurality of second banks which are different from the plurality of first banks, the memory controller including a holding circuit configured to hold a read and/or write access request which comprises a target memory device and a target bank, and a control circuit configured to select an access request from the access requests held in the holding circuit and to issue a read command and/or a write command, and the control method comprising: controlling, in a case where a first access request to the first memory device is selected and then a first read command and/or write command is issued, to prohibit to select a second access request to the second memory for a predetermined period after elapse of a tCCD period (Column to Column Delay period) of the first read command and/or write command, wherein the predetermined period after elapse of a tCCD period is greater than the tCCD period,
and controlling, in a case where the first access request to the first memory device is selected and then the first read command and/or write command is issued, to permit to select a third access request to the first memory for the predetermined period.