Memory device, operating method of memory device and memory system including a first subblock configured to perform operations independently of a second subblock

1 . A memory device comprising:

a plurality of memory blocks, each memory block of the plurality of memory blocks including

a first subblock configured to store first data in triple level cell (TLC) units or quad level cell (QLC) units; and

a second subblock configured to perform an erase operation independently of the first subblock and store second data in units of single level cells (SLCs),

wherein each memory block comprises a first memory stack and a second memory stack that are connected between a common source line and a plurality of bit lines and the first memory stack and the second memory stack are vertically stacked, and wherein the first subblock corresponds to the first memory stack, and the second subblock corresponds to the second memory stack, and

wherein, in response to receiving a write operation performing request from a host device, the write operation performing request corresponding to the first data, the memory device is configured to perform a first write operation on the second subblock of a first memory block, the first write operation writing the second data into the second subblock of the first memory block, and in response to the first write operation being performed, the memory device is configured to perform a first read operation on the second data in the second subblock of the first memory block, and

wherein the memory device is configured to perform a second write operation on the first subblock of a selected memory block of the plurality of memory blocks in response to the first read operation being performed on the second data in the second subblock of the first memory block, the second write operation writing the first data into the first subblock of the selected memory block, and

wherein the memory device is configured to store meta data in the second subblock of a second memory block.

2 . The memory device of claim 1 , wherein the second subblock of the first memory block includes a data buffer region.

3 . The memory device of claim 1 , wherein the selected memory block is the first memory block, and wherein the second write operation is performed on the first subblock of the first memory block.

4 . The memory device of claim 3 , wherein the memory device is configured to perform the erase operation on the second subblock of the first memory block in response to the second write operation being performed.

5 . The memory device of claim 1 , wherein the selected memory block is the second memory block, and wherein the second write operation is performed on the first subblock of the second memory block.

6 . The memory device of claim 5 , wherein the memory device is configured to perform the erase operation on the second subblock of the first memory block in response to the second write operation being performed.

7 . The memory device of claim 1 , wherein the memory device is configured to use the second subblock of the first memory block as a data buffer region for data to be stored in the first subblock of the selected memory block, and to use the second subblock of the second memory block as a meta region in which the meta data is stored.

8 . The memory device of claim 1 , wherein the second subblock of the second memory block includes a meta region.

9 . A method of operating a memory device including a plurality of memory blocks, each memory block of the plurality of memory blocks including a first subblock and a second subblock, the plurality of memory blocks including a first memory block and a second memory block, the method comprising:

in response to receiving a write operation performing request corresponding to a first data, performing a first write operation on the second subblock of the first memory block, the first write operation writing second data into the second subblock of the first memory block;

in response to the first write operation being performed, performing a first read operation on the second data in the second subblock of the first memory block;

in response to the first read operation being performed on the second data in the second subblock of the first memory block, performing a second write operation on the first subblock of a selected memory block of the plurality of memory blocks, the second write operation writing the first data into the first subblock of the selected memory block; and

storing meta data in the second subblock of the second memory block,

wherein the first subblock stores the first data in triple level cell (TLC) or quad level cell (QLC) units, and the second subblock stores the second data in units of single level cells (SLCs) and performs an erase operation independently of the first subblock, and

wherein each memory block comprises a first memory stack and a second memory stack connected between a common source line and a plurality of bit lines and the first memory stack and the second memory stack are vertically stacked, the first subblock corresponding to the first memory stack and the second subblock corresponding to the second memory stack.

10 . The method of claim 9 , wherein the selected memory block is the first memory block, and wherein the second write operation is performed on the first subblock of the first memory block.

11 . The method of claim 10 , further comprising:

performing the erase operation on the second subblock of the first memory block in response to performing the second write operation.

12 . The method of claim 9 , wherein the selected memory block is the second memory block, and wherein the second write operation is performed on the first subblock of the second memory block.

13 . The method of claim 12 , further comprising:

performing the erase operation on the second subblock of the first memory block in response to performing the second write operation.

14 . The method of claim 9 , wherein the second subblock of the second memory block includes a meta region.

15 . The method of claim 9 , wherein the second subblock of the first memory block includes a data buffer region.

16 . A memory system comprising:

a memory device including a plurality of memory blocks; and

a host controlling the memory device,

wherein each memory block of the plurality of memory blocks includes,

a first subblock configured to store first data in triple level cell (TLC) or quad level cell (QLC) units, and

a second subblock configured to perform an erase operation independently of the first subblock and store second data in units of single level cells (SLCs),

wherein each memory block comprises a first memory stack and a second memory stack that are connected between a common source line and a plurality of bit lines and the first memory stack and the second memory stack are vertically stacked, and wherein the first subblock corresponds to the first memory stack, and the second subblock corresponds to the second memory stack,

wherein the plurality of memory blocks includes a first memory block and a second memory block,

wherein the host is configured to control the memory device such that in response to the memory device receiving a write operation performing request from the host, the write operation performing request corresponding to the first data, the memory device is configured to perform a first write operation on the second subblock of the first memory block, the first write operation writing the second data into the second subblock of the first memory block, and in response to the first write operation, the memory device is configured to perform a first read operation on the second data in the second subblock of the first memory block,

wherein in response to the first read operation being performed on the second data in the second subblock of the first memory block, the memory device is configured to perform a second write operation on the first subblock of a selected memory block of the plurality of memory blocks, the second write operation writing the first data into the first subblock of the first memory block, and

wherein the memory device is configured to store meta data in the second subblock of the second memory block.

17 . The memory system of claim 16 , wherein the second subblock of the first memory block includes a data buffer region.

18 . The memory system of claim 16 , wherein the selected memory block is the first memory block, and wherein the second write operation is performed on the first subblock of the first memory block.

19 . The memory system of claim 16 , wherein the selected memory block is the second memory block, and wherein the second write operation is performed on the first subblock of the second memory block.

20 . The memory system of claim 16 , wherein the second subblock of the second memory block includes a meta region.