Persistent XSPI STT-MRAM with optional erase operation
The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.
1 . A memory device, comprising:
a plurality of memory arrays; and
a non-volatile erase bit value register,
wherein the memory device is configured to:
receive a program command;
assign an erase bit value a first state or a second state based on a criticality of a performance, a criticality of an operation time, or a need to emulate a Not-Or (NOR) memory device;
receive the erase bit value from the non-volatile erase bit value register; and
prior to a programming step, wherein the programming step includes programming one or more of the plurality of memory arrays based on the program command:
activating, based on a determination that the erase bit value is in the first state, an optional erase command to erase the one or more of the plurality of memory arrays, or
not activating, based on a determination that the erase bit value is in the second state, the optional erase command thereby not erasing the one or more of the plurality of memory arrays.
2 . The memory device of claim 1 , wherein the memory device further comprises a bias system connected to the plurality of memory arrays.
3 . The memory device of claim 1 , wherein the memory device further comprises a bias system connected to the plurality of memory arrays, the bias system comprising one or more anti-fuse blocks.
4 . The memory device of claim 1 , wherein the memory device further comprises:
a bias system connected to the plurality of memory arrays, the bias system comprising one or more anti-fuse blocks;
an interface connected to the one or more anti-fuse blocks, an interface supply, and one or more inputs or outputs of the memory device.
5 . The memory device of claim 1 , further configured to:
receive a write enable command at the memory device prior to programming the one or more of the plurality of memory arrays; and
receive a write disable command at the memory device after programming the one or more of the plurality of memory arrays.
6 . The memory device of claim 1 , wherein the memory device comprises an expanded serial peripheral interface (xSPI) magnetoresistive random-access memory (MRAM) device.
7 . A memory device, comprising:
a plurality of memory arrays; and
a configuration register configured to store an erase bit value,
wherein the memory device is configured to:
receive a command to program one or more of the plurality of memory arrays;
assign the erase bit value in the configuration register a first state or a second state, wherein assigning the erase bit value includes:
if a performance or an operation time is critical, assigning the erase bit value in the erase bit value register a first state, or
if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state; and
optionally erase the one or more of the plurality of memory arrays prior to programming, wherein optionally erasing the one or more of the plurality of memory arrays comprises:
when the erase bit value is in the first state, erasing the one or more of the plurality of memory arrays, or
when the erase bit value is in the second state, not erasing the one or more of the plurality of memory arrays.
8 . The memory device of claim 7 , wherein the memory device further comprises a bias system connected to the plurality of memory arrays.
9 . The memory device of claim 7 , wherein the memory device further comprises a bias system connected to the plurality of memory arrays, the bias system comprising one or more anti-fuse blocks.
10 . The memory device of claim 7 , wherein the memory device further comprises:
a bias system connected to the plurality of memory arrays, the bias system comprising one or more anti-fuse blocks;
an interface connected to the one or more anti-fuse blocks, an interface supply, and one or more inputs or outputs of the memory device.
11 . The memory device of claim 7 , further configured to:
receive a write enable command at the memory device prior to programming the one or more of the plurality of memory arrays; and
receive a write disable command at the memory device after programming the one or more of the plurality of memory arrays.
12 . The memory device of claim 7 , wherein the memory device comprises an expanded serial peripheral (xSPI) magnetoresistive random-access memory (MRAM) device.
13 . A method for programming a memory device comprising a plurality of memory arrays, the method comprising:
receiving a command to program one or more of the plurality of memory arrays;
assigning an erase bit value register an erase bit value, the erase bit value having a first state or a second state, wherein assigning the erase bit value includes:
if a performance or an operation time is critical, assigning the erase bit value in the erase bit value register a first state, or
if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state; and
when the erase bit value is in the first state, activating an optional erase command to erase the one or more of the plurality of memory arrays prior to programming the one or more of the plurality of memory arrays, or
when the erase bit value is in the second state, not erasing the one or more of the plurality of memory arrays prior to programming the one or more of the plurality of memory arrays.
14 . The method of claim 13 , wherein, when the erase bit value is in the first state, the programming of the one or more of the plurality of memory arrays comprises programming the one or more of the plurality of memory arrays after erasing the one or more of the plurality of memory arrays.
15 . The method of claim 13 , wherein the memory device comprises a bias system connected to the plurality of memory arrays.
16 . The method of claim 13 , wherein the memory device comprises a bias system connected to the plurality of memory arrays, the bias system comprising one or more anti-fuse blocks.
17 . The method of claim 13 , wherein the memory device comprises a bias system connected to an array supply or a bias supply.
18 . The method of claim 13 , wherein the memory device comprises an expanded serial peripheral interface (xSPI) magnetoresistive random-access memory (MRAM) device.
19 . The method of claim 13 , wherein the memory device comprises an error correction code datapath corresponding to each of the plurality of memory arrays, and
wherein the memory device comprises an interface connected to one or more anti-fuse blocks.
20 . The method of claim 13 , further comprising:
receiving a write enable command at the memory device prior to programming the one or more of the plurality of memory arrays; and
receiving a write disable command at the memory device after programming the one or more of the plurality of memory arrays.