Digit-recurrence selection constants
A data processing apparatus to perform a digit-recurrence operation on an input value comprises receiver circuitry for receiving a remainder value of a previous iteration of the digit-recurrence operation. Comparison circuitry performs comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation and outputs the next digit of the result of the digit-recurrence operation based on the comparisons. Each of the selection constants is associated with one of the available digits and an input parameter. Storage circuitry stores a subset of the selection constants, the subset of the selection constants excluding an excluded selection constant from the selection constants, which is associated with an excluded digit from the available digits.
1 . A data processing apparatus to perform a digit-recurrence operation on an input value, comprising:
receiver circuitry configured to receive a remainder value of a previous iteration of the digit-recurrence operation; and
comparison circuitry configured to perform comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation-with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation, and to output the next digit of the result of the digit-recurrence operation based on the comparisons, wherein each of the selection constants is associated with one of the available digits and an input parameter, and wherein in a division-mode of operation, the digit-recurrence operation is a division digit-recurrence operation, the input parameter is a divisor, and the selection constants comprise division selection constants, and in a square-root-mode of operation, the digit-recurrence operation is a square-root digit-recurrence operation, the input parameter is a partial root, and the selection constants comprise square-root selection constants; and
storage circuitry configured to store at least a subset of the division selection constants or the square-root selection constants, and offsets indicative of how to convert between the division selection constants and the square-root selection constants.
2 . The data processing apparatus according to claim 1 , further comprising:
conversion circuitry configured to generate an excluded selection constant from the selection constants stored in the storage circuitry.
3 . The data processing apparatus according to claim 2 , wherein
the conversion circuitry is configured to generate the excluded selection constant by performing a selective inversion of a sign of one of the selection constants stored in the storage circuitry.
4 . The data processing apparatus according to claim 3 , wherein
the one of the selection constants is associated with a same input parameter and a different one of the available digits as the excluded selection constant.
5 . The data processing apparatus according to claim 3 , wherein
the storage circuitry is configured to store, for the selection constants, an exception flag to indicate whether the selective inversion is to take place to generate the excluded selection constant.
6 . The data processing apparatus according to claim 1 , wherein
the digit-recurrence operation is the square-root digit-recurrence operation; and
the input parameter is the partial root.
7 . The data processing apparatus according to claim 1 , wherein
the digit-recurrence operation is the division digit-recurrence operation; and
the input parameter is the divisor.
8 . The data processing apparatus according to claim 2 , wherein
each of the selection constants are the selection constants.
9 . The data processing apparatus according to claim 8 , wherein
the conversion circuitry is configured to generate the excluded selection constant in the division-mode of operation by performing a selective inversion of a sign of one of the division selection constants.
10 . The data processing apparatus according to claim 8 , wherein
the conversion circuitry is configured to generate the excluded selection constant in the square-root-mode of operation by referencing one of the division selection constants.
11 . The data processing apparatus according to claim 9 , wherein
the storage circuitry is configured to store, for the selection constants, an exception flag to indicate whether the selective inversion is to take place to generate the excluded selection constant.
12 . The data processing apparatus according to claim 1 , wherein
the digit-recurrence operation is in radix-8.
13 . A method of data processing to perform a digit-recurrence operation on an input value, comprising:
receiving a remainder value of a previous iteration of the digit-recurrence operation; and
performing comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation,
outputting the next digit of the result of the digit-recurrence operation based on the comparisons, wherein each of the selection constants is associated with one of the available digits and an input parameter, and wherein in a division-mode of operation, the digit-recurrence operation is a division digit-recurrence operation, the input parameter is a divisor, and the selection constants comprise division selection constants, and in a square-root-mode of operation, the digit-recurrence operation is a square-root digit- recurrence operation, the input parameter is a partial root, and the selection constants comprise square-root selection constants; and
storing at least a subset of the division selection constants or the square-root selection constants, and offsets indicative of how to convert between the division selection constants and the square-root selection constants.
14 . A non-transitory computer-readable medium to store computer-readable code for fabrication of a data processing apparatus to perform a digit-recurrence operation on an input value, the data processing apparatus comprising:
receiver circuitry configured to receive a remainder value of a previous iteration of the digit-recurrence operation; and
comparison circuitry configured to perform comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation, and to output the next digit of the result of the digit-recurrence operation based on the comparisons, wherein each of the selection constants is associated with one of the available digits and an input parameter, and wherein in a division-mode of operation, the digit-recurrence operation is a division digit-recurrence operation, the input parameter is a divisor, and the selection constants comprise division selection constants, and in a square-root-mode of operation, the digit-recurrence operation is a square-root digit-recurrence operation, the input parameter is a partial root, and the selection constants comprise square-root selection constants; and
storage circuitry configured to store at least a subset of the division selection constants or the square-root selection constants, and offsets indicative of how to convert between the division selection constants and the square-root selection constants.