Nested loop control
A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.
1 . A device comprising:
a non-transitory memory storing instructions for execution by at least one processor core, wherein the instructions include:
a first instruction that, when executed, causes the at least one processor core to retrieve a predicate value from a buffer and store the predicate value in a register; and
a second instruction that, when executed, causes the at least one processor core to determine whether to perform an operation based on the predicate value.
2 . The device of claim 1 , wherein:
the buffer is configured to store each of a set of values that includes the predicate value at a respective offset; and
the first instruction specifies the predicate value by specifying the respective offset of the predicate value within the buffer.
3 . The device of claim 1 , wherein:
the buffer is associated with a level of a set of nested loops; and
the first instruction specifies the level associated with the buffer.
4 . The device of claim 1 , wherein:
the predicate value is a first predicate value; and
the instructions include a third instruction that, when executed causes:
a loop counter to transition; and
a second predicate value to be stored in the buffer.
5 . The device of claim 4 , wherein the second predicate value is determined based on whether an output of the loop counter is zero.
6 . The device of claim 1 , wherein the buffer is a first-in-first-out buffer.
7 . The device of claim 6 , wherein the buffer includes a set of serially-coupled latches.
8 . The device of claim 1 comprising an integrated circuit that includes the non-transitory memory and the at least one processor core.
9 . A device comprising:
a controller that includes a buffer; and
a set of processor cores that includes a register, wherein the set of processor cores is configured to:
in response to a first instruction:
cause the controller to provide a predicate value from the buffer; and
store the predicate value in the register; and
in response to a second instruction, determine whether to perform an operation based on the predicate value.
10 . The device of claim 9 , wherein the first instruction specifies to provide the predicate value by specifying an offset associated with the predicate value in the buffer.
11 . The device of claim 9 , wherein:
the buffer is associated with a level of a set of nested loops; and
the first instruction specifies the level associated with the buffer.
12 . The device of claim 9 , wherein:
the controller further comprises a loop counter;
the predicate value is a first predicate value; and
the instructions include a third instruction that, when executed causes:
the loop counter to transition; and
a second predicate value to be stored in the buffer.
13 . The device of claim 12 , wherein the second predicate value is determined based on whether an output of the loop counter is zero.
14 . The device of claim 9 , wherein the buffer is a first-in-first-out buffer.
15 . The device of claim 14 , wherein:
the buffer includes a set of serially-coupled latches; and
the controller includes a multiplexer coupled to the set of serially-coupled latches.
16 . A method comprising:
receiving, by at least one processor core of a set of processor cores, a first instruction;
based on the first instruction:
retrieving a predicate value from a buffer; and
storing the predicate value in a register of the set of processor cores;
receiving, by at least one processor core of the set of processor cores, a second instruction; and
based on the second instruction, determining whether to perform an operation based on the predicate value.
17 . The method of claim 16 , wherein the first instruction specifies the predicate value by specifying an offset associated with the predicate value as stored within the buffer.
18 . The method of claim 16 , wherein:
the buffer is associated with a level of a set of nested loops; and
the first instruction specifies the level associated with the buffer.
19 . The method of claim 16 , wherein:
the predicate value is a first predicate value; and
the method further comprises:
receiving, by at least one processor core of a set of processor cores, a third instruction; and
based on the third instruction:
causing a loop counter to transition; and
causing a second predicate value to be stored in the buffer.
20 . The method of claim 19 , wherein the second predicate value is determined based on whether an output of the loop counter is zero.