Un-mark instructions on an instruction match to reduce resources required to match a group of instructions

1 . A computer-implemented method of performing instruction marking in a computer processor architecture, the computer-implemented method comprising:

fetching, by a fetching unit in the computer processor architecture, instructions from a memory unit, wherein each instruction of the fetched instructions comprises bits associated with a primary operation code of a respective instruction of the fetched instructions, bits associated with information of the respective instruction, and bits associated with an instruction type of the respective instruction;

determining instruction groups for marking the fetched instructions;

matching the fetched instructions to the instruction groups for the marking of the fetched instructions, wherein each instruction group of the instruction groups comprises a respective plurality of instructions of the fetched instructions;

for each instruction group of the instruction groups, marking the respective plurality of instructions of a corresponding instruction group of the instruction groups, wherein

the respective plurality of instructions is marked using a single marking resource instead of marking each instruction of the respective plurality of instructions individually using a respective marking resource of a plurality of marking resources for processing in the computer processor architecture,

the single marking resource is associated with a matching mask that includes the bits associated with the primary operation code, and

the bits associated with the primary operation code are same for each instruction of the respective plurality of instructions;

for each instruction group of the instruction groups, selectively unmarking a set of instructions from the marked respective plurality of instructions in the corresponding instruction group, wherein each instruction of the set of instructions is unmarked using a respective unmarking resource of a set of unmarking resources; and

forwarding the marked respective plurality of instructions and the unmarked set of instructions to a queue of instructions for the processing in the computer processor architecture.

2 . The computer-implemented method of claim 1 , wherein the marking of the respective plurality of instructions includes identifying each instruction of the respective plurality of instructions based on an instruction operation type.

3 . The computer-implemented method of claim 2 , wherein the marking of the respective plurality of instructions further includes setting the instruction operation type of each instruction of the respective plurality of instructions.

4 . The computer-implemented method of claim 3 , wherein the selectively unmarking of the set of instructions includes setting one or more instruction operation types of each instruction of the set of instructions, wherein the one or more instruction operation types exclude the instruction operation type.

5 . The computer-implemented method of claim 1 , wherein the marked respective plurality of instructions and the unmarked set of instructions share the primary operation code.

6 . The computer-implemented method of claim 1 , wherein the unmarked set of instructions is processed without an interrupt.

7 . The computer-implemented method of claim 1 , further comprising:

setting, during the marking of the respective plurality of instructions, the bits associated with the primary operation code, wherein the bits associated with the primary operation code are same for each instruction of the respective plurality of instructions; and

setting, to an ignore status, the bits associated with the information of each instruction of the respective plurality of instructions and the bits associated with the instruction type of each instruction of the respective plurality of instructions.

8 . The computer-implemented method of claim 1 , wherein the marking of the respective plurality of instructions includes:

setting the matching mask to mark the respective plurality of instructions sharing the same primary operation code;

setting the matching mask to match an instruction operation type of each instruction of the respective plurality of instructions sharing the same primary operation code; and

setting the matching mask to ignore instruction operation types of each instruction of the respective plurality of instructions sharing the same primary operation code, wherein the instruction operation types exclude the instruction operation type.

9 . The computer-implemented method of claim 1 , wherein

each matching mask, of a plurality of matching masks associated with the plurality of marking resources, includes the bits associated with the primary operation code and the bits associated with the instruction type, and

the bits associated with the instruction type are different for each instruction of the respective plurality of instructions.

10 . A computer-implemented method of performing instruction marking in a computer processor architecture, the computer-implemented method comprising:

fetching, by a fetching unit in the computer processor architecture, instructions from a memory unit, wherein each instruction of the fetched instructions comprises bits associated with a primary operation code of a respective instruction of the fetched instructions, bits associated with information of the respective instruction, and bits associated with an instruction type of the respective instruction;

identifying an instruction operand type of each instruction of the fetched instructions;

determining instruction groups, for marking of the fetched instructions, based on the identified instruction operand type of each instruction of the fetched instructions;

generating a marking unit mask for the marking of the fetched instructions;

generating an unmarking unit mask for unmarking of a set of instructions;

matching the fetched instructions to the instruction groups, wherein each instruction group of the instruction groups comprises a respective plurality of instructions of the fetched instructions;

for each instruction group of the instruction groups, marking the respective plurality of instructions of a corresponding instruction group of the instruction groups, wherein

the respective plurality of instructions is marked using a single marking resource instead of marking each instruction of the respective plurality of instructions individually using a respective marking resource of a plurality of marking resources for processing in the computer processor architecture,

the marking unit mask associated with the single marking resource includes the bits associated with the primary operation code, and

the bits associated with the primary operation code are same for each instruction of the respective plurality of instructions;

for each instruction group of the instruction groups, selectively unmarking the set of instructions from the marked respective plurality of instructions, wherein a first instruction of the set of instructions is unmarked using the unmarking unit mask; and

forwarding the marked respective plurality of instructions and the unmarked set of instructions to a queue of instructions for the processing in the computer processor architecture.

11 . The computer-implemented method of claim 10 , wherein instruction operand types for the unmarking exclude the instruction operand type for the marking.

12 . The computer-implemented method of claim 10 , wherein the marked respective plurality of instructions and the unmarked set of instructions share the primary operation code.

13 . The computer-implemented method of claim 10 , further comprising processing the unmarked set of instructions without an interrupt.

14 . The computer-implemented method of claim 10 , wherein the generating of the marking unit mask includes setting, to an ignore status, the bits associated with the information of each instruction of the respective plurality of instructions and the bits associated with the instruction type of each instruction of the respective plurality of instructions.

15 . A computer processor architecture, comprising:

a first memory cache;

an instruction fetching unit configured to retrieve instructions from the first memory cache, wherein each instruction of the retrieved instructions comprises bits associated with a primary operation code of a respective instruction of the retrieved instructions, bits associated with information of the respective instruction, and bits associated with an instruction type of the respective instruction;

a matching unit;

an instruction marking unit, wherein the instruction marking unit is configured to:

designate one or more instruction operation types for marking of the retrieved instructions;

determine whether the instructions retrieved by the instruction fetching unit include the one or more instruction operation types; and

add marks to a plurality of instructions of the retrieved instructions based on the plurality of instructions including the one or more instruction operation types, wherein

the plurality of instructions represents an instruction group,

the plurality of instructions is marked using a single marking resource instead of marking each instruction of the plurality of instructions individually using a respective marking resource of a plurality of marking resources for processing in the computer processor architecture,

the single marking resource is associated with a matching mask that includes the bits associated with the primary operation code, and

the bits associated with the primary operation code are same for each instruction of the plurality of instructions:

an instruction unmarking unit, wherein

the instruction unmarking unit is configured to selectively unmark a set of instructions from the marked plurality of instructions by removing the marking from the set of instructions, and

each instruction of the set of instructions is unmarked using a respective unmarking resource of a set of unmarking resources; and

a second memory cache operable to:

receive the marked plurality of instructions;

receive the unmarked set of instructions; and

forward the marked plurality of instructions and the unmarked set of instructions for the processing.

16 . The computer processor architecture of claim 15 , further comprising a decoder unit configured to:

decode the marked plurality of instructions; and

ignore the unmarked set of instructions.

17 . The computer processor architecture of claim 15 , wherein the instruction marking unit is further configured to set, to an ignore status, the bits associated with the information of each instruction of the plurality of instructions and the bits associated with the instruction type of each instruction of the plurality of instructions.

18 . The computer processor architecture of claim 15 , wherein one or more instruction operation types for the unmarking exclude the one or more instruction operation types set for the marking.

19 . The computer processor architecture of claim 15 , wherein the marked plurality of instructions and the unmarked set of instructions share the primary operation code.

20 . The computer processor architecture of claim 15 , wherein the matching unit is configured to:

set the matching mask, for use by the instruction marking unit, to mark the plurality of instructions sharing the same primary operation code;

set the matching mask to match the one or more instruction operation types of each instruction of the plurality of instructions sharing the same primary operation code; and

set the matching mask to ignore instruction operation types of each instruction of the plurality of instructions sharing the same primary operation code, wherein the instruction operation types exclude the one or more instruction operation types.