Microprocessor that performs mid-fetch block restart abort processing

1 . A microprocessor, comprising:

an instruction cache;

a prediction circuit configured to:

perform a first lookup of a fetch block start address (FBSA) in a fetch block predictor (FBP);

detect that the FBSA hits on an entry of the FBP that predicts a fetch block (FBlk) of architectural instructions is present in a program instruction stream, wherein the FBlk comprises a sequential run of architectural instructions; and

use the hit entry to generate a first FBlk descriptor (FBD) that describes the FBlk;

an instruction fetch circuit configured to use the first FBD to fetch the architectural instructions of the FBlk from the instruction cache for execution; and

a control circuit configured to:

receive from an execution circuit an abort request that indicates an architectural instruction of the FBlk caused a need for an abort;

determine, in response to the abort request, an abort point that separates the FBlk into a former portion and a latter portion;

flush the latter portion of the FBlk;

allow the former portion of the FBlk to execute; and

provide the abort point to the prediction circuit and signal the prediction circuit to restart at the FBSA of the FBlk;

wherein the prediction circuit is further configured to, in response to the signal:

perform a second lookup of the FBSA of the FBlk in the FBP;

detect that the FBSA hits on the same entry of the FBP that predicts the FBlk is present in the program instruction stream; and

use the hit entry to generate a second FBD that describes at least the latter portion of the FBlk;

wherein the instruction fetch circuit is further configured to use the second FBD to fetch at least the latter portion of the FBlk from the instruction cache for execution; and

wherein the microprocessor executes the latter portion of the FBlk but does not re-execute the former portion of the FBlk.

2 . The microprocessor of claim 1 ,

wherein the microprocessor refrains from creating a new entry in the FBP in response to the abort request.

3 . The microprocessor of claim 1 ,

wherein the second FBD describes only the latter portion of the FBlk.

4 . The microprocessor of claim 3 ,

wherein the first FBD specifies a length and the FBSA of the FBlk; and

wherein the second FBD specifies a length and an FBSA of the latter portion of the FBlk such that the instruction fetch circuit uses the second FBD to fetch only the latter portion of the FBlk from the instruction cache.

5 . The microprocessor of claim 1 ,

wherein both the first FBD and the second FBD describe the FBlk; and

wherein the instruction fetch circuit is further configured to, after using the second FBD to fetch the FBlk from the instruction cache, discard the former portion of the FBlk and to provide only the latter portion of the FBlk for execution.

6 . The microprocessor of claim 1 , further comprising:

a decode circuit configured to:

receive the architectural instructions of the FBlk from the instruction fetch circuit;

discard the former portion of the FBlk;

decode the architectural instructions of the latter portion of the FBlk into micro-operations; and

provide only the decoded micro-operations of the latter portion of the FBlk for execution.

7 . The microprocessor of claim 1 , further comprising:

a decode circuit configured to:

decode into first micro-operations the architectural instructions of the FBlk fetched using the first FBD;

dispatch the first micro-operations to the execution circuit for execution;

decode into second micro-operations the architectural instructions of the FBlk fetched using the second FBD;

discard the second micro-operations corresponding to the former portion of the FBlk; and

dispatch the second micro-operations corresponding to the latter portion of the FBlk for execution.

8 . The microprocessor of claim 1 ,

wherein the architectural instruction of the FBlk that caused a need for an abort is a load instruction; and

wherein a cause of the abort request is a misprediction by load value predictor with respect to the load instruction.

9 . The microprocessor of claim 1 ,

wherein the architectural instruction of the FBlk that caused a need for an abort is a load instruction; and

wherein a cause of the abort request is a store-to-load-forwarding violation with respect to the load instruction.

10 . The microprocessor of claim 1 ,

wherein the architectural instruction of the FBlk that caused a need for an abort is a load instruction; and

wherein a cause of the abort request is a misprediction by a store-to-load forwarding bypass predictor with respect to the load instruction.

11 . The microprocessor of claim 1 , further comprising:

branch history; and

branch predictors;

wherein the prediction circuit is further configured to, in parallel with each of the first and second lookups, perform corresponding first and second lookups in the branch predictors of the FBSA in combination with the branch history to determine, in conjunction with the hit entry of the FBP, a successor FBSA produced by the FBlk; and

wherein the prediction circuit is further configured to, in response to the signal, restore the branch history to correspond to its state when the first lookup in the branch predictors was performed.

12 . A method, comprising:

in a microprocessor comprising:

an instruction cache;

a prediction circuit;

an instruction fetch circuit; and

a control circuit;

by the prediction circuit:

performing a first lookup of a fetch block start address (FBSA) in a fetch block predictor (FBP);

detecting that the FBSA hits on an entry of the FBP that predicts a fetch block (FBlk) of architectural instructions is present in a program instruction stream, wherein the FBlk comprises a sequential run of architectural instructions; and

using the hit entry to generate a first FBlk descriptor (FBD) that describes the FBlk;

using, by the instruction fetch circuit, the first FBD to fetch the architectural instructions of the FBlk from the instruction cache for execution; and

by the control circuit:

receiving from an execution circuit an abort request that indicates an architectural instruction of the FBlk caused a need for an abort;

determining, in response to the abort request, an abort point that separates the FBlk into a former portion and a latter portion;

flushing the latter portion of the FBlk;

allowing the former portion of the FBlk to execute; and

providing the abort point to the prediction circuit and signaling the prediction circuit to restart at the FBSA of the FBlk;

by the prediction circuit in response to the signal:

performing a second lookup of the FBSA of the FBlk in the FBP;

detecting that the FBSA hits on the same entry of the FBP that predicts the FBlk is present in the program instruction stream; and

using the hit entry to generate a second FBD that describes at least the latter portion of the FBlk;

using, by the instruction fetch circuit, the second FBD to fetch at least the latter portion of the FBlk from the instruction cache for execution; and

executing, by the microprocessor, the latter portion of the FBlk but not re-executing the former portion of the FBlk.

13 . The method of claim 12 , further comprising:

refraining from creating a new entry in the FBP in response to the abort request.

14 . The method of claim 12 ,

wherein the second FBD describes only the latter portion of the FBlk.

15 . The method of claim 14 ,

wherein the first FBD specifies a length and the FBSA of the FBlk; and

wherein the second FBD specifies a length and an FBSA of the latter portion of the FBlk such that the instruction fetch circuit uses the second FBD to fetch only the latter portion of the FBlk from the instruction cache.

16 . The method of claim 12 , further comprising:

wherein both the first FBD and the second FBD describe the FBlk; and

discarding, by the instruction fetch circuit after using the second FBD to fetch the FBlk from the instruction cache, the former portion of the FBlk and providing only the latter portion of the FBlk for execution.

17 . The method of claim 12 , further comprising:

by a decode circuit of the microprocessor:

receiving the architectural instructions of the FBlk from the instruction fetch circuit;

discarding the former portion of the FBlk;

decoding the architectural instructions of the latter portion of the FBlk into micro-operations; and

providing only the decoded micro-operations of the latter portion of the FBlk for execution.

18 . The method of claim 12 , further comprising:

by a decode circuit of the microprocessor:

decoding into first micro-operations the architectural instructions of the FBlk fetched using the first FBD;

dispatching the first micro-operations to the execution circuit for execution;

decoding into second micro-operations the architectural instructions of the FBlk fetched using the second FBD;

discarding the second micro-operations corresponding to the former portion of the FBlk; and

dispatching the second micro-operations corresponding to the latter portion of the FBlk for execution.

19 . The method of claim 12 ,

wherein the architectural instruction of the FBlk that caused a need for an abort is a load instruction; and

wherein a cause of the abort request is a misprediction by load value predictor with respect to the load instruction.

20 . The method of claim 12 ,

wherein the architectural instruction of the FBlk that caused a need for an abort is a load instruction; and

wherein a cause of the abort request is a store-to-load-forwarding violation with respect to the load instruction.

21 . The method of claim 12 ,

wherein the architectural instruction of the FBlk that caused a need for an abort is a load instruction; and

wherein a cause of the abort request is a misprediction by a store-to-load forwarding bypass predictor with respect to the load instruction.

22 . The method of claim 12 , further comprising:

wherein the microprocessor further includes:

branch history; and

branch predictors;

by the prediction circuit in parallel with each of the first and second lookups:

perform corresponding first and second lookups in the branch predictors of the FBSA in combination with the branch history to determine, in conjunction with the hit entry of the FBP, a successor FBSA produced by the FBlk; and

restoring, by the prediction circuit in response to the signal, the branch history to correspond to its state when the first lookup in the branch predictors was performed.

23 . A non-transitory computer-readable medium having instructions stored thereon that are capable of configuring a microprocessor, wherein the instructions configure the microprocessor to perform a method comprising:

in a microprocessor comprising:

an instruction cache;

a prediction circuit;

an instruction fetch circuit; and

a control circuit;

by the prediction circuit:

performing a first lookup of a fetch block start address (FBSA) in a fetch block predictor (FBP);

detecting that the FBSA hits on an entry of the FBP that predicts a fetch block (FBlk) of architectural instructions is present in a program instruction stream, wherein the FBlk comprises a sequential run of architectural instructions; and

using the hit entry to generate a first FBlk descriptor (FBD) that describes the FBlk;

using, by the instruction fetch circuit, the first FBD to fetch the architectural instructions of the FBlk from the instruction cache for execution; and

by the control circuit:

receiving from an execution circuit an abort request that indicates an architectural instruction of the FBlk caused a need for an abort;

determining, in response to the abort request, an abort point that separates the FBlk into a former portion and a latter portion;

flushing the latter portion of the FBlk;

allowing the former portion of the FBlk to execute; and

providing the abort point to the prediction circuit and signaling the prediction circuit to restart at the FBSA of the FBlk;

by the prediction circuit in response to the signal:

performing a second lookup of the FBSA of the FBlk in the FBP;

detecting that the FBSA hits on the same entry of the FBP that predicts the FBlk is present in the program instruction stream; and

using the hit entry to generate a second FBD that describes at least the latter portion of the FBlk;

using, by the instruction fetch circuit, the second FBD to fetch at least the latter portion of the FBlk from the instruction cache for execution; and

executing, by the microprocessor, the latter portion of the FBlk but not re-executing the former portion of the FBlk.