Accelerator with configurable circuit to perform different operation types

1 . An accelerator, comprising:

a calculating circuit configured to

implement an operation related to an elliptic curves algorithm, wherein the operation related to the elliptic curves algorithm, wherein the calculating circuit comprises a general logic circuit composed of a basic logic circuit, the general logic circuit is to perform an operation of different operation types in response to different inputs; and the accelerator further comprises:

an acquiring circuit, configured to acquire a target microcode instruction corresponding to a target type operation to be implemented, the target microcode instruction is generated according to the target type operation, wherein the target microcode instruction is used to indicate target input data required to perform the general logic circuit to implement the target type operation;

a parsing circuit configured to parse the target microcode instruction to obtain a parsing result corresponding to the target input data; and

a controlling circuit configured to, in response to the parsing result, control the calculating circuit to enable the calculating circuit to acquire the target input data and run the general logic circuit based on the target input data so as to complete the target type operation;

wherein the accelerator is communicatively connected to a central processing unit (CPU), and the accelerator or the CPU is configured to:

acquire an operation program that performs the target type operation on at least one operand comprised in the operation program, and

generate the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program;

wherein the operation program further comprises a dot multiplication scalar and the target type operation is a dot multiplication operation on the dot multiplication scalar and the at least one operand;

wherein the accelerator or the CPU is further configured to generate a plurality of target microcode instructions for implementing the dot multiplication operation according to the dot multiplication scalar and the at least one operand comprised in the operation program; and

wherein the accelerator is further configured to execute each target microcode instruction in the plurality of target microcode instructions, so as to complete the dot multiplication operation.

2 . The accelerator according to claim 1 , wherein the accelerator further comprises a data storage space, the data storage space stores a preset operand used to generate a microcode instruction, and

wherein the accelerator or the CPU is further configured to:

store the at least one operand obtained by parsing in the data storage space; and

generate the target microcode instruction according to the target type operation based on a storage address of the at least one operand and/or the preset operand in the data storage space.

3 . The accelerator according to claim 2 , wherein the parsing result comprises a storage address of the target input data; and

the controlling circuit is configured to, according to the storage address of the target input data, the calculating circuit to read the target input data from the data storage space and perform the target type operation based on the target input data.

4 . The accelerator according to claim 1 , wherein the basic logic circuit is configured to perform a modular addition operation and a modular multiplication operation, and the general logic circuit is configured to perform a modular multiplication on a calculation result of two modular addition operations.

5 . The accelerator according to claim 4 , wherein an input required by the general logic circuit comprises a first input, a second input, a third input and a fourth input; and

wherein an operation process of the general logic circuit comprises:

performing a modular addition operation on the first input and the second input to obtain a first modular addition result;

performing a modular addition operation on the third input and the fourth input to obtain a second modular addition result; and

performing a modular multiplication operation on the first modular addition result and the second modular addition result to obtain a final calculation result.

6 . The accelerator according to claim 5 , wherein the at least one operand comprises a first operand and a second operand; and

wherein the accelerator or the CPU is further configured to:

in response to the target type operation being a modular addition operation on the first operand and the second operand, set the first input to the first operand, set the second input to the second operand, set the third input to 1 and set the fourth input to 0;

in response to the target type operation being a modular subtraction operation on the first operand and the second operand, set the first input to the first operand, set the second input to the second operand and adjust a symbol corresponding to the second input to a negative sign, set the third input to 1 and set the fourth input to 0;

in response to the target type operation being a modular multiplication operation on the first operand and the second operand, set the first input to the first operand, and set the third input to the second operand, and set the second input and the fourth input to 0;

in response to the target type operation being a modular addition squared operation on the first operand and the second operand, set the first input and the third input to the first operand, and set the second input and the fourth input to the second operand; and

generate the target microcode instruction according to the first input, the second input, the third input and the fourth input.

7 . The accelerator according to claim 5 , wherein the modular multiplication operation comprises a modular multiplication operation of a first type and a modular multiplication operation of a second type; and

wherein the accelerator further comprises:

a data storage space;

wherein the data storage space stores a preset constant;

wherein the preset constant is used to mutually convert between a first data field and a second data field;

wherein the first data field is used for the modular multiplication operation of the first type and the second data field is used for the modular multiplication operation of the second type;

wherein the calculating circuit is configured to:

in response to the modular multiplication operation converting from the first type to the second type, acquire the preset constant and convert the first data field into the second data field according to the preset constant to implement the modular multiplication operation of the second type; and

in response to the modular multiplication operation converting from the second type to the first type, acquire the preset constant and convert the second data field into the first data field according to the preset constant to implement the modular multiplication operation of the first type.

8 . The accelerator according to claim 1 ,

wherein the controlling circuit comprises a breakpoint circuit configured to interrupt the calculating circuit from executing a subsequent microcode instruction in response to reception of an interrupt instruction, so as to enable a debugging circuit corresponding to the accelerator to acquire a calculation result of the calculating circuit, and output a comparison result between the calculation result and a preset calculation result.

9 . The accelerator according to claim 1 , wherein the accelerator is a coprocessor implemented based on a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) for accelerating the elliptic curves algorithm; or an auxiliary accelerating module implemented based on a CPU for performing an algorithm acceleration for the elliptic curves algorithm.

10 . An electronic device, comprising the accelerator according to claim 1 .

11 . An accelerating method, applied to an accelerator,

wherein the accelerator comprises a calculating circuit

configured to implement an operation related to an elliptic curves algorithm,

wherein the calculating circuit comprises a general logic circuit composed of a basic logic circuit, and

wherein the general logic circuit is configured to perform an operation of different operation types in response to different inputs, and the accelerating method comprising:

acquiring a target microcode instruction corresponding to a target type operation to be implemented, the target microcode instruction is generated according to the target type operation, wherein the target microcode instruction is used to indicate target input data required to perform the general logic circuit to implement the target type operation;

parsing the target microcode instruction to obtain a parsing result corresponding to the target input data; and

in response to the parsing result, controlling the calculating circuit to enable the calculating circuit to acquire the target input data and run the general logic circuit based on the target input data so as to complete the target type operation,

wherein the accelerator is communicatively connected to a central processing unit (CPU), and the accelerating method further comprises:

acquiring an operation program that performs the target type operation on at least one operand comprised in the operation program, and

generating the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program,

wherein the operation program further comprises a dot multiplication scalar and the target type operation is a dot multiplication operation on the dot multiplication scalar and the at least one operand,

wherein the generating the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program comprises generating a plurality of target microcode instructions for implementing the dot multiplication operation according to the dot multiplication scalar and the at least one operand comprised in the operation program, and

wherein the accelerating method further comprises executing each target microcode instruction in the plurality of target microcode instructions, so as to complete the dot multiplication operation.

12 . The accelerating method according to claim 11 , wherein the accelerator further comprises a data storage space configured to store a preset operand used to generate a microcode instruction, and

wherein the generating the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program comprises:

storing the at least one operand obtained by parsing in the data storage space, and

generating the target microcode instruction according to the target type operation, based on a storage address of the at least one operand and/or the preset operand in the data storage space,

wherein the parsing result comprises a storage address of the target input data, and

wherein, in response to the parsing result, controlling the calculating circuit to enable the calculating circuit to acquire the target input data and run the general logic circuit based on the target input data so as to complete the target type operation comprises:

controlling, according to the storage address of the target input data, the calculating circuit to read the target input data from the data storage space and performing the target type operation based on the target input data.

13 . The accelerating method according to claim 11 , wherein the basic logic circuit is to perform a modular addition operation and a modular multiplication operation, and the general logic circuit is to perform a modular multiplication on a calculation result of two modular addition operations;

wherein an input required by the general logic circuit comprises a first input, a second input, a third input and a fourth input; and

wherein an operation process of the general logic circuit comprises:

performing a modular addition operation on the first input and the second input to obtain a first modular addition result;

performing a modular addition operation on the third input and the fourth input to obtain a second modular addition result; and

performing a modular multiplication operation on the first modular addition result and the second modular addition result to obtain a final calculation result.

14 . The accelerating method according to claim 13 , wherein the at least one operand comprises a first operand and a second operand, and

wherein the accelerating method further comprises:

in response to the target type operation being a modular addition operation on the first operand and the second operand, setting the first input to the first operand, setting the second input to the second operand, setting the third input to 1 and setting the fourth input to 0;

in response to the target type operation being a modular subtraction operation on the first operand and the second operand, setting the first input to the first operand, setting the second input to the second operand and adjusting a symbol corresponding to the second input to a negative sign, setting the third input to 1 and setting the fourth input to 0;

in response to the target type operation being a modular multiplication operation on the first operand and the second operand, setting the first input to the first operand, and setting the third input to the second operand, and setting the second input and the fourth input to 0;

in response to the target type operation being a modular addition squared operation on the first operand and the second operand, setting the first input and the third input to the first operand, and setting the second input and the fourth input to the second operand; and

generating the target microcode instruction according to the first input, the second input, the third input and the fourth input.

15 . The accelerating method according to claim 13 ,

wherein the modular multiplication operation comprises a modular multiplication operation of a first type and a modular multiplication operation of a second type,

wherein the accelerator further comprises:

a data storage space,

wherein the data storage space stores a preset constant,

wherein the preset constant is used to mutually convert between a first data field and a second data field,

 wherein the first data field is used for the modular multiplication operation of the first type and the second data field is used for the modular multiplication operation of the second type, and

wherein the accelerating method further comprises:

in response to the modular multiplication operation converting from the first type to the second type, acquiring the preset constant and converting the first data field into the second data field according to the preset constant to implement the modular multiplication operation of the second type, and

in response to the modular multiplication operation converting from the second type to the first type, acquiring the preset constant and converting the second data field into the first data field according to the preset constant to implement the modular multiplication operation of the first type.

16 . A non-transitory computer-readable storage medium, wherein an accelerator in a computer comprises a memory, a processor, and a computer program stored on the memory and operable on the processor, wherein the processor, when running the computer program, is configured to: implement an operation related to an elliptic curves algorithm, wherein the operation related to the elliptic curves algorithm comprises a general logic operation composed of a basic logic operation, the general logic operation is to perform an operation of different operation types in response to different inputs, and the non-transitory computer-readable storage medium stores a computer program, the accelerator, when executing the computer program, is configured to:

acquire a target microcode instruction corresponding to a target type operation to be implemented, the target microcode instruction is generated according to the target type operation, wherein the target microcode instruction is used to indicate target input data required to perform the general logic operation to implement the target type operation;

parse the target microcode instruction to obtain a parsing result corresponding to the target input data; and

in response to the parsing result, acquire the target input data and run the general logic operation based on the target input data so as to complete the target type operation;

wherein the accelerator is communicatively connected to a central processing unit (CPU), and the accelerator or the CPU is configured to:

acquire an operation program that performs the target type operation on at least one operand comprised in the operation program, and

generate the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program;

wherein the operation program further comprises a dot multiplication scalar and the target type operation is a dot multiplication operation on the dot multiplication scalar and the at least one operand;

wherein the accelerator or the CPU is further configured to generate a plurality of target microcode instructions for implementing the dot multiplication operation according to the dot multiplication scalar and the at least one operand comprised in the operation program; and

wherein the accelerator is further configured to execute each target microcode instruction in the plurality of target microcode instructions, so as to complete the dot multiplication operation.