NUMA multi-core processor switching between lock modes, operating method, and instructions therefor

1 . A multi-core processor, comprising:

a plurality of central processing unit (CPU) cores configured to form a plurality of non-uniform memory access (NUMA) nodes,

wherein:

by executing a lock-application instruction, different processes running on different CPU cores applying for a lock of a shared computing resource are queued, to be locked with the shared computing resource to gain access rights to the shared computing resource;

the execution of the lock-application instruction involves monitoring a competition-level indicator;

in response to the competition-level indicator satisfying a first switching condition, the lock of the shared computing resource is switched from a primitive lock mode to a NUMA lock mode;

in the primitive lock mode, the processes follow a first-in and first-out rule to gain the lock of the shared computing resource, regardless of their NUMA nodes;

in the NUMA lock mode, the processes on a same NUMA node with the shared computing resource gain the lock of the shared computing resource first; and

after the first switching condition is satisfied, through the execution of the lock-application instruction, subsequent processes applying for the lock are not permitted to enter the queue until all processes already queued gain a primitive lock for operations in turn, and then the subsequent processes are queued to gain a NUMA lock.

2 . The multi-core processor as claimed in claim 1 , wherein:

the competition-level indicator includes information about depth data, wherein the depth data shows the number of processes that have applied for the lock and have not been unlocked yet; and

in response to depth data exceeding a threshold a predetermined number of times, the lock of the shared computing resource is switched from the primitive lock mode to the NUMA lock mode.

3 . The multi-core processor as claimed in claim 2 , wherein:

the depth data is increased every time a process applies for the lock of the shared computing resource, and is decreased every time a process is unlocked.

4 . The multi-core processor as claimed in claim 3 , wherein:

the depth data is presented in a primitive lock data structure; and

the lock-application instruction invokes management of the depth data.

5 . The multi-core processor as claimed in claim 4 , wherein:

M and N are numbers; and

an instruction operand of the lock-application instruction is M+N bits, the high N bits are for accumulation of the depth data, and the low M bits realize a comparison-with-exchange instruction.

6 . The multi-core processor as claimed in claim 5 , wherein the lock-application instruction is:

CMPXCHG_INC r/m64, r32, wherein

the high 32 bits of a register, r/m64, are for accumulation;

the low 32 bits of r/m64 are compared with a register, EAX;

if the low 32 bits of r/m64 are equal to EAX, a register, ZF, is set to 1, r/m64 is loaded into a register, RAX, and a register, r32, is loaded into the low 32 bits of r/m64; and

if the low 32 bits of r/m64 are not equal to EAX, ZF is cleared to 0, and r/m64 is loaded into RAX.

7 . The multi-core processor as claimed in claim 4 , wherein:

M and N are numbers; and

an instruction operand of the lock-application instruction is M+N bits, the high N bits are for accumulation of the depth data, and the low M bits realize an exchange instruction.

8 . The multi-core processor as claimed in claim 7 , wherein the lock-application instruction is:

CMPNEXCHGINC r/m64, r32, wherein

the low 32 bits of a register, r/m64, are compared with a register, EAX;

if the low 32 bits of r/m64 are equal to EAX, a register, ZF, is set to 1, and r/m64 is loaded into a register, RAX; and

if the low 32 bits of r/m64 are not equal to EAX, ZF is cleared to 0, accumulation is performed on the high 32 bits of r/m64, r/m64 is loaded into RAX, and a register, r32, is loaded into the low 32 bits of r/m64.

9 . The multi-core processor as claimed in claim 4 , wherein:

by executing an unlocking instruction, a process gaining the lock releases the lock to the queued processes;

M and N are numbers; and

an instruction operand of the unlocking instruction is M+N bits, the high N bits are for decreasing the depth data, and the low M bits realize a comparison-with-exchange instruction.

10 . The multi-core processor as claimed in claim 9 , wherein the unlocking instruction is:

CMPXCHG_DEC r/m64, r32, wherein

the high 32 bits of a register, r/m64, are decremented;

the low 32 bits of r/m64 are compared with a register, EAX;

if the low 32 bits of r/m64 are equal to EAX, a register, ZF, is set to 1, r/m64 is loaded into a register, RAX, and a register, r32, is loaded into the lower 32 bits of r/m64; and

if the low 32 bits of r/m64 are not equal to EAX, ZF is cleared to 0, and r/m64 is loaded into RAX.

11 . The multi-core processor as claimed in claim 1 , wherein:

the competition-level indicator further carries an over-threshold number that shows how many times data representing a competition level exceeds a threshold; and

in response to the over-threshold number showing that the data representing the competition level exceeds a threshold a predetermined number of times, the lock of the shared computing resource is switched from the primitive lock mode to the NUMA lock mode.

12 . The multi-core processor as claimed in claim 1 , wherein:

the lock-application instruction is an equal-without-exchange instruction, which stops an exchange action when a lock variable is equal to a default value, otherwise, the equal-without-exchange instruction behaves as an exchange instruction; and

after the first switching condition is satisfied, all queued processes gain the primitive lock for operations in turn and, the lock variable is set to the default value to prevent pushing more processes into the queue until NUMA lock resource is ready.

13 . The multi-core processor as claimed in claim 1 , wherein:

in response to the competition-level indicator satisfying a second switching condition, the lock of the shared computing resource is switched from the NUMA lock mode to the primitive lock mode.

14 . The multi-core processor as claimed in claim 13 , wherein:

the competition-level indicator shows a number of processes applying for locks on each NUMA node; and

when a total number of processes applying for locks on each NUMA node is lower than a threshold, the second switching condition is satisfied.

15 . The multi-core processor as claimed in claim 13 , wherein:

a NUMA lock data structure includes lock information; and

if the lock information matches unique tag information about a primitive lock mapped to a NUMA lock presented in the NUMA lock data structure, the NUMA lock is reliable; otherwise, the NUMA lock is unreliable.

16 . The multi-core processor as claimed in claim 15 , wherein:

the lock information is address information; and

if the lock information matches address information of the primitive lock mapped to the NUMA lock, the NUMA lock is reliable; otherwise, the NUMA lock is unreliable.

17 . The multi-core processor as claimed in claim 15 , wherein:

a high-bit comparison-with-exchange instruction is executed to determine whether the lock information matches address information of the primitive lock mapped to the NUMA lock.

18 . The multi-core processor as claimed in claim 15 , wherein the lock-application instruction is:

CMPNEXCHG r/m64, r16, wherein

a register, r/m64, is compared with a register, RAX in their high M bits, M is a number, and N is another number, where M+N is 64 or 32; and

when the high M bits of r/m64 is different from the high M bits of a register, EAX, or low N bits of r/m64 are a preset locking value, 0xffff, a register ZF is cleared to 0, and r/m64 is loaded into RAX and; otherwise, ZF is set to 1, r/m64 is loaded into EAX, and a register, r16, is exchanged with the low N bits of r/m64.

19 . The multi-core processor as claimed in claim 18 , wherein:

after the second switching condition is satisfied, processes already queued gain the NUMA lock for operations in turn, low bits of a lock variable are set to an expected locking value, a primitive lock mark is deleted from high bits of the lock variable, and thereby subsequent processes are not allowed to be pushed into the queue again for a primitive lock till primitive lock resource is ready.

20 . The multi-core processor as claimed in claim 15 , wherein:

the lock-application instruction is a high-bit comparison-with-exchange instruction, which exchanges data when having high bits that are equal to a primitive lock mark and low bits that are different from an expected locking value.

21 . The multi-core processor as claimed in claim 15 , wherein:

the lock-application instruction is a high-bit comparison-with-exchange instruction, which stops exchanging data when having high bits that are different from a primitive lock mark and low bits that show an expected locking value.

22 . A method for operating a multi-core processor, comprising:

allocating a plurality of central processing unit (CPU) cores to configure a plurality of non-uniform memory access (NUMA) nodes;

providing a lock-application instruction;

executing the lock-application instruction to queue different processes running on different CPU cores applying for a lock of the shared computing resource to be locked with the shared computing resource to gain access rights to the shared computing resource;

monitoring a competition-level indicator during the execution of the lock- application instruction;

determining that the competition-level indicator satisfies a first switching condition;

and switching the lock of the shared computing resource from a primitive lock mode to a NUMA lock mode;

wherein in the primitive lock mode, the processes follow the first-in and first-out rule to gain the lock of the shared computing resource, regardless of their NUMA nodes; wherein in the NUMA lock mode, the processes on a NUMA node with the shared computing resource gain the lock of the shared computing resource first; and

after the first switching condition is satisfied, refusing entry to the queue for subsequent processes applying for the lock through the execution of the lock-application instruction until processes already queued gain a primitive lock for operations in turn, and then queuing the subsequent processes to gain a NUMA lock.

23 . The method as claimed in claim 22 , further comprising:

determining whether the competition-level indicator satisfies a second switching condition; and

switching the lock of the shared computing resource from the NUMA lock mode to the primitive lock mode when it is determined that the competition-level indicator satisfies the second switching condition.

24 . The method as claimed in claim 23 , wherein

a NUMA lock data structure includes lock information;

determining the NUMA lock is reliable when the lock information matches unique tag information about a primitive lock mapped to a NUMA lock presented in the NUMA lock data structure; and otherwise determining the NUMA lock is unreliable.