Data structure for a buffer memory in a multi-producer multi-consumer system

1 . A buffer architecture for a multi-producer multi-consumer system, the buffer architecture comprising:

an executing computer; and

a memory component accessible by the executing computer;

wherein:

the memory component includes:

a buffer memory that the executing computer is configured to access as a plurality of slots in each of which data is storable by the executing computer and which are each assigned a respective one of a plurality of unique identifiers; and

three index queues managed by the executing computer and representing respective ones of three states into which the slots can be transitioned; the three queues include:

a first queue that stores a first subset of the identifiers, which correspond to a subset of the slots, which are in a first state of the three states of being inactive and therefore inaccessible for writing thereto and inaccessible for reading therefrom by the executing computer;

a second queue that stores a second subset of the identifiers, which correspond to a subset of the slots, which are in a second state of the three states of having been written to by a producer and of awaiting reading by a consumer; and

a third queue that stores a third subset of the identifiers, which correspond to a subset of the slots, which are in a third state of the three states of being currently usable for a new write operation by a producer; and

the executing computer is configured to access the buffer memory based on the identifiers stored in the first queue, the second queue, and the third queue such that:

at each moment in time, each of the identifiers is stored in exactly one of the first, second, or third queues, thereby assigning the respective slots identified by the respective identifiers to one of the three states;

with respect to a respective one of the slots:

a write access to the respective one of the slots of the buffer memory is obtained by the executing computer dequeuing the corresponding identifier of the respective slot from the third queue; and

a read access to the respective slot is obtained by the executing computer dequeuing the corresponding identifier of the respective slot from the second queue; and

the identifiers are movable between the queues according to the following transitions:

(a) from the third queue to the second queue in response to a write operation by the executing computer into the corresponding slot;

(b) to the third queue after a read operation by the executing computer from the corresponding slot that took place by a dequeuing from the second queue; and

(c) from the first queue to the third queue in response to the corresponding slot being activated for use as part of the buffer for writing thereto and reading therefrom, a number of the identifiers being held in the third queue thereby defining a dynamically adjustable usable capacity of the buffer memory that is accessible by the executing computer.

2 . The buffer architecture as recited in claim 1 , wherein each of the identifiers is represented using an integer value.

3 . The buffer architecture as recited in claim 2 , wherein the integer value represents a corresponding one of the slots and a write-in cycle.

4 . The buffer architecture as recited in claim 1 , wherein each of the first queue, the second queue, and the third queue includes a variable for representing an instantaneous write-in position and a variable for representing an instantaneous read position, the variables each being represented using a respective integer value that represents both the respective write-in position or read position and an instantaneous cycle.

5 . The buffer architecture as recited in claim 1 , wherein the first queue, the second queue, and the third queue have the same capacity as one another.

6 . The buffer architecture as recited in claim 1 , wherein the first queue, the second queue, and the third queue fulfill a FIFO principle.

7 . The buffer architecture as recited in claim 1 , wherein the buffer architecture is configured for execution of lock-free, atomic push operations and lock-free atomic pop operations on the first queue, the second queue, and the third queue.

8 . The buffer architecture as recited in claim 1 , wherein, for each of the slots, a read access and/or a write access to the respective slot is possible only with possession of the identifier assigned to the respective slot.