Data storage device and method for generating read threshold voltages
A bit error rate (BER) estimation scan (BES) typically uses static read thresholds during the scan process. These fixed thresholds might not adapt to variations in memory cell characteristics, leading to suboptimal BER estimation and error correction. The embodiments presented herein can be used to address this problem by providing a hybrid variation of BES and on-chip (e.g., in a controller ASIC) threshold voltage (Vth) tracking. In one example, BER results from BES failing pages are used to update Vth tracking parameters. In this way, BER results can be used to identify the most unreliable memory pages, and the Vth tracking parameters can be updated to reduce the BER for those pages. Other examples are provided.
1 . A data storage device comprising:
a memory; and
one or more processors, individually or in combination, configured to:
(a) obtain a bit error rate (BER) estimation scan (BES) result from a page in the memory;
(b) update threshold voltage (Vth) tracking parameters for scan voltage, number of scans, and voltage size between scans with the BES result from the page in the memory;
(c) repeating (a) and (b) until the updated Vth tracking parameters converge to a local minima; and
(d) use the updated Vth tracking parameters to read the page in the memory, wherein using the updated Vth tracking parameters to read the page in the memory reduces the BER of the page.
2 . The data storage device of claim 1 , wherein the one or more processors comprise an integrated circuit and the Vth tracking parameters are updated on-chip in the integrated circuit.
3 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to perform a soft-bit decode operation.
4 . The data storage device of claim 1 , wherein the BES is performed during a time tag update.
5 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.
6 . In a data storage device comprising a memory, a method comprising:
(a) obtaining a bit error rate (BER) estimation scan (BES) result from each of a plurality of pages of the memory after a default read of the plurality of pages of the memory;
(b) updating threshold voltage (Vth) tracking parameters for scan voltage, number of scans, and voltage size between scans with the BES results from the plurality of pages in the memory;
(c) repeating (a) and (b) until the updated Vth tracking parameters converge to a local minima;
(d) using the updated Vth tracking parameters to read one of the plurality of pages in the memory, wherein using the updated Vth tracking parameters to read the one of the plurality of pages in the memory reduces the BER of the one of the plurality of pages in the memory.
7 . The method of claim 6 , wherein the Vth tracking parameters are updated on-chip in an integrated circuit in the data storage device.
8 . The method of claim 6 , further comprising performing a soft-bit decode operation.
9 . The method of claim 6 , further comprising performing the BES by:
reading data from each of the plurality of page at different voltage levels; and
comparing the read data to expected data.
10 . The method of claim 6 , wherein the BES is performed during a time tag update.
11 . The method of claim 6 , wherein the memory comprises a three-dimensional memory.
12 . A data storage device comprising:
a memory; and
means for:
(a) obtaining a bit error rate (BER) estimation scan (BES) result from a page in the memory;
(b) updating threshold voltage (Vth) tracking parameters for scan voltage, number of scans, and voltage size between scans with the BES result from the page in the memory;
(c) repeating (a) and (b) until the updated Vth tracking parameters converge to a local minima; and
(d) using the updated Vth tracking parameters to read the page in the memory, wherein using the updated Vth tracking parameters to read the page in the memory reduces the BER of the page.