IP Library › Granted Patent US 12693970

Granted Patent B2

US 12693970 · App. 18/902,243 · Granted Jul 28, 2026

Serial peripheral interface to multiple memory types

Inventor: Kanda K. Palanisamy (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

G06F12/0246

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Quick Facts

Patent No.: US 12693970
App. No.: 18/902,243
Granted: Jul 28, 2026
Kind: B2

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Abstract

An apparatus includes one or more controller circuits that are configured to be coupled to a first memory that implements random access and a second memory that implements serial access. A processing unit is configured to generate a map indicating a first set of addresses allocated to the first memory and a second set of addresses allocated to the second memory. The processing unit configures the controller circuit(s) to selectively access either the first memory or the second memory based on the map. In some cases, the first memory is a NOR-based memory, the second memory is a NAND flash memory, and the controller circuit is a serial peripheral interface (SPI) controller circuit. Selectively accessing the first memory or the second memory can include asserting a signal on a first or second chip select pin.

Claims (41)

1 . An apparatus comprising:

at least one controller circuit configured to be coupled to at least one first memory that implements random access and at least one second memory that implements serial access; and

at least one processing unit configured to:

generate a map indicating a first set of addresses allocated to the at least one first memory and a second set of addresses allocated to the at least one second memory, and

configure the at least one controller circuit to selectively access the at least one first memory or the at least one second memory based on the map,

wherein selectively accessing the at least one first memory or the at least one second memory comprises formatting a memory access request for either serial access or random access based on the map.

2 . The apparatus of claim 1 , wherein the at least one first memory is a NOR-based memory, wherein the at least one second memory is a NAND flash memory, and wherein the at least one controller circuit is at least one serial peripheral interface (SPI) controller circuit.

3 . The apparatus of claim 1 , wherein the at least one controller circuit is configured to receive the memory access request including a memory address and to selectively access the at least one first memory or the at least one second memory based on a comparison of the memory address and the map.

4 . The apparatus of claim 3 , wherein the at least one controller circuit is configured to selectively access the at least one first memory in response to the memory address being in the first set of addresses and to selectively access the at least one second memory in response to the memory address being in the second set of addresses.

5 . The apparatus of claim 4 , wherein the at least one processing unit is configured to provide first information representing a first type of the at least one first memory and second information representing a second type of the at least one second memory to the at least one controller circuit.

6 . An apparatus comprising:

at least one controller circuit configured to be coupled to at least one first memory that implements random access and at least one second memory that implements serial access; and

at least one processing unit configured to:

to provide first information representing a first type of the at least one first memory and second information representing a second type of the at least one second memory to the at least one controller circuit, wherein the first information comprises information indicating at least one of a first chip select pin corresponding to the at least one first memory, at least one size of the at least one first memory, and at least one command supported by the at least one first memory, and wherein the second information comprises information indicating at least one of a second chip select pin corresponding to the at least one second memory, at least one size of the at least one second memory, and at least one command supported by the at least one second memory;

generate a map indicating a first set of addresses allocated to the at least one first memory and a second set of addresses allocated to the at least one second memory; and

configure the at least one controller circuit to selectively access the at least one first memory or the at least one second memory based on the map.

7 . The apparatus of claim 6 , wherein the at least one controller circuit is configured to assert a signal on the first chip select pin in response to a received memory address being in the first set of addresses, and wherein the at least one controller circuit is configured to assert a signal on the second chip select pin in response to the received memory address being in the second set of addresses.

8 . The apparatus of claim 7 , further comprising:

the at least one first memory, wherein the at least one first memory is configured to receive a memory access request from the at least one controller circuit in response to the signal being asserted on the first chip select pin and to bypass receiving the memory access request from the at least one controller circuit in response to the signal being asserted on the second chip select pin.

9 . The apparatus of claim 8 , wherein the at least one second memory is configured to receive the memory access request from the at least one controller circuit in response to the signal being asserted on the second chip select pin and to bypass receiving the memory access request from the at least one controller circuit in response to the signal being asserted on the first chip select pin.

10 . A method comprising:

generating a map indicating a first set of addresses allocated to at least one first memory that implements random access and a second set of addresses allocated to at least one second memory that implements serial access; and

in response to receiving a memory access request, selectively accessing the at least one first memory or the at least one second memory based on the map, wherein selectively accessing the at least one first memory or the at least one second memory comprises formatting a memory access request for either serial access or random access based on the map.

11 . The method of claim 10 , wherein the at least one first memory is a NOR-based memory, and wherein the at least one second memory is a NAND flash memory.

12 . The method of claim 10 , further comprising:

receiving the memory access request including a memory address; and

selectively accessing the at least one first memory or the at least one second memory based on a comparison of the memory address and the map.

13 . The method of claim 12 , wherein selectively accessing the at least one first memory or the at least one second memory comprises selectively accessing the at least one first memory in response to the memory address being in the first set of addresses and selectively accessing the at least one second memory in response to the memory address being in the second set of addresses.

14 . The method of claim 10 , wherein formatting the memory access request comprises formatting memory access requests to the at least one first memory based on first information indicating at least one size of the at least one first memory or at least one command supported by the at least one first memory and formatting memory requests to the at least one second memory based on second information indicating at least one size of the second memory or at least one command supported by the at least one second memory.

15 . The method of claim 10 , wherein selectively accessing the at least one first memory or the at least one second memory comprises asserting a signal on at least one first chip select pin in response to a received memory address being in the first set of addresses or asserting a signal on at least one second chip select pin in response to the received memory address being in the second set of addresses.

16 . The method of claim 15 , further comprising:

receiving, at the at least one first memory, the memory access request in response to the signal being asserted on the at least one first chip select pin; and

bypassing receiving the memory access request at the at least one first memory in response to the signal being asserted on the at least one second chip select pin.

17 . The method of claim 15 , further comprising:

receiving, at the at least one second memory, the memory access request in response to the signal being asserted on the at least one second chip select pin; and

bypassing receiving the memory access request at the at least one second memory in response to the signal being asserted on the at least one first chip select pin.

18 . An apparatus comprising:

at least one processing unit configured to generate a map indicating a first set of addresses allocated to at least one first memory that implements random access and a second set of addresses allocated to at least one second memory that implements serial access; and

at least one controller circuit configured to access the at least one first memory or access the at least one second memory based on the map, wherein the at least one controller circuit is configured to access the at least one first memory by formatting a memory access request to the at least one first memory for random access and is configured to access the at least one second memory by formatting a memory access request to the at least one second memory for serial access.

19 . The apparatus of claim 18 , wherein the at least one controller circuit comprises a first controller circuit configured to randomly access the at least one first memory in response to receiving the memory access request comprising an address in the first set of addresses, and wherein the at least one controller circuit comprises a second controller circuit configured to serially access the at least one second memory in response to receiving a memory access request comprising an address in the second set of addresses.

20 . The apparatus of claim 18 , wherein the at least one processing unit is configured to boot up a processing system using the at least one first memory prior to generating the map.