Caching data of memory rows
View Patent ↗In some examples, a memory controller includes a cache and an interface to a communication channel that is connected to a memory module. The memory controller receives an alert based on a counter in the memory module breaching a threshold, where the counter is associated with a row of memory cells in the memory module, and the alert indicates a frequent activation of the row of memory cells. Based on the alert, the memory controller stores, in the cache, data stored in the row of memory cell.
1 . A memory controller comprising:
a cache; and
an interface to a communication channel that is connected to a memory module,
the memory controller to:
receive, at the memory controller over the communication channel, an alert based on a counter in the memory module breaching a threshold, the counter associated with a row of memory cells in the memory module, and the alert indicating a frequent activation of the row of memory cells; and
based on the alert;
access, over the communication channel, a register of the memory module to determine a memory address of the row of memory cells, and
retrieve, from the memory module, data of the row of memory cells identified by the memory address from the register; and
store the retrieved data in the cache.
2 . The memory controller of claim 1 , wherein the memory controller is to:
in response to a request to access the row of memory cells, retrieve responsive data from the cache without activating the row of memory cells in the memory module.
3 . The memory controller of claim 1 , wherein the memory address in the register of the memory module was added to the register by the memory module based on the memory module detecting the counter breaching the threshold.
4 . The memory controller of claim 3 , wherein the memory controller is to provide the memory address to an operating system (OS) memory manager for a reallocation of memory regions to mitigate the frequent activation of the row of memory cells.
5 . The memory controller of claim 1 , wherein the memory controller comprises a counter to track a quantity of accesses of the data of the row of memory cells in the cache.
6 . The memory controller of claim 1 , wherein the threshold is stored in a register of the memory module.
7 . The memory controller of claim 6 , wherein the memory controller is to program the threshold in the register of the memory module.
8 . The memory controller of claim 1 , wherein the cache is to store data of N rows of memory cells in the memory module, where N is greater than or equal to 1.
9 . The memory controller of claim 1 , wherein the cache comprises a first cache segment, and the communication channel is a first communication channel connected to a first set of memory devices in the memory module, wherein the first cache segment is to store data of a row of memory cells of any of the memory devices of the first set of memory devices, and wherein the interface couples the memory controller over a second communication channel to a second set of memory devices in the memory module, and the cache further comprises:
a second cache segment to store data of a row of memory cells of any of the memory devices in the second set of memory devices.
10 . The memory controller of claim 9 , wherein the memory controller is to:
receive a further alert based on a further counter in a further memory device of the second set of memory devices breaching the threshold, the further counter associated with a given row of memory cells in the memory module, and the further alert indicating a frequent activation of the given row of memory cells, and
based on the further alert, store, in the second cache segment, data of the given row of memory cells.
11 . The memory controller of claim 1 , wherein the memory controller is to:
after storing the data of the row of memory cells in a cache line of the cache:
monitor a frequency of access of the data in the cache line; and
based on the monitored frequency satisfying an inactivity threshold, invalidate the cache line containing the data of the row of memory cells.
12 . The memory controller of claim 11 , further comprising:
a row access counter to count a quantity of accesses of the data in the cache line, wherein the monitoring of the frequency of access is based on the count of the row access counter, wherein the row access counter is different from the counter in the memory module.
13 . A memory device comprising:
a channel interface to a communication channel that is connected to a memory controller;
an array of memory cells;
a plurality of counters to track activations of respective rows of memory cells in the array of memory cells;
a register to store a memory address of a given row of the rows of memory cells responsive to a count of a given counter associated with the given row breaching a threshold,
wherein the memory device is to, based on an access of the register by the memory controller, send, from the memory device to the memory controller over the communication channel, the memory address of the given row.
14 . The memory device of claim 13 , wherein the memory device is to send an alert to the memory controller responsive to the count of the given counter breaching the threshold.
15 . The memory device of claim 14 , wherein the register is accessible by the memory controller for the memory controller to determine the memory address of the given row of memory cells.
16 . The memory device of claim 13 , wherein the register is a first register, the memory device further comprising:
a second register to store the threshold.
17 . The memory device of claim 16 , wherein the threshold in the second register is adjustable by the memory controller.
18 . A method of an electronic device, comprising:
detecting that a count of a counter in a memory module and associated with a row of memory cells in the memory module has breached a threshold;
based on the count of the counter breaching the threshold, issuing, by the memory module, an indication to a memory controller over a communication channel connecting the memory controller and the memory module, and storing, by the memory module in a register of the memory module, a row memory address of the row of memory cells;
retrieving, by the memory controller, the row memory address of the row of memory cells from the register over the communication channel;
retrieving, by the memory controller from the memory module, data of the row of memory cells identified by the row memory address from the register; and
caching, by the memory controller, the retrieved data of the row of memory cells in a cache of the memory controller.
19 . The method of claim 18 , further comprising:
receiving, at the memory controller, a request for data in the row of memory cells;
retrieving, at the memory controller, the requested data from the cache; and
sending, by the memory controller, the requested data retrieved from the cache to an entity that sent the request to the memory controller.
20 . The method of claim 18 , further comprising:
sending, by the memory controller, the row memory address to an operating system (OS) memory manager; and
reallocating memory regions in the memory module based on the row memory address received from the memory controller.