Systems, methods, and apparatus for memory loading in a storage device

1 . A device comprising:

memory media configured as a cache;

storage media;

a buffer; and

at least one circuit configured to perform one or more operations comprising:

receiving memory address information corresponding to data to be loaded to the cache;

parsing one or more addresses from the memory address information;

storing the one or more addresses in the buffer;

determining an availability of the device to load data to the memory media; and

loading the data to the memory media, from the storage media, corresponding to the one or more addresses in the buffer.

2 . The device of claim 1 , wherein the memory address information is first memory address information;

wherein the data is first data; and

wherein the at least one circuit is further configured to perform one or more operations comprising:

receiving a memory access request comprising second memory address information;

determining to load second data from the storage media based on a priority of the memory access request; and

loading the second data to the memory media, from the storage media, corresponding to the second memory address information.

3 . The device of claim 1 , wherein loading the data comprises:

obtaining at least one address from the memory address information; and

adding the at least one address to the buffer.

4 . The device of claim 1 , wherein the memory address information comprises an indication of a length of addresses and at least one address.

5 . The device of claim 1 , wherein the memory address information comprises at least one address and an indication of a number of addresses.

6 . The device of claim 1 , wherein the at least one circuit is further configured to perform one or more operations comprising:

receiving an instruction to make the buffer available; and

making the buffer available.

7 . The device of claim 1 , wherein the at least one circuit is further configured to perform one or more operations comprising:

receiving an instruction to make the memory media available; and

making the memory media available.

8 . The device of claim 1 , wherein the at least one circuit comprises a control register configured to perform one or more operations comprising:

determining, based on the control register, a status of the buffer; and

modifying, based on the status, operations of the at least one circuit.

9 . A method comprising:

receiving memory address information corresponding to data to be loaded to a cache;

parsing one or more addresses from the memory address information;

storing the one or more addresses in a buffer;

determining an availability to load data to memory media; and

loading the data to the memory media, from storage media, based on the memory address information in the buffer.

10 . The method of claim 9 ,

wherein the memory address information is first memory address information;

wherein the data is first data; and

wherein the method further comprises:

receiving a memory access request comprising second memory address information;

determining to load second data from the storage media based on a priority of the memory access request; and

loading the second data to the memory media, from the storage media, based on the second memory address information.

11 . The method of claim 9 , wherein loading the data comprises:

obtaining at least one address from the memory address information; and

adding the at least one address to the buffer.

12 . The method of claim 9 , wherein the memory address information comprises an indication of a length of addresses and at least one address.

13 . The method of claim 9 , wherein the memory address information comprises at least one address and an indication of a number of addresses.

14 . The method of claim 9 , further comprising:

receiving a request to make the buffer available; and

making the buffer available.

15 . The method of claim 9 , further comprising:

determining a status of the buffer; and

modifying, based on the status, operations on the buffer.

16 . A system comprising:

a host device comprising an application and a thread, wherein the thread comprises memory address information corresponding to data to be loaded to a cache for the application; and

a storage device comprising:

memory media configured as the cache;

storage media;

a buffer; and

at least one circuit configured to perform one or more operations comprising:

receiving the memory address information;

parsing one or more addresses from the memory address information;

storing the memory address information in the buffer;

determining an availability of the storage device to load data to the memory media; and

loading the data to the memory media, from the storage media, based on the one or more addresses in the buffer.

17 . The system of claim 16 , wherein the at least one circuit is further configured to perform one or more operations comprising:

receiving a memory access request comprising second memory address information;

determining to load second data based on the memory access request; and

loading the second data to the memory media, from the storage media, based on the second memory address information.

18 . The system of claim 16 , wherein the memory address information comprises an indication of a length of addresses and at least one address.

19 . The system of claim 16 , wherein the memory address information comprises at least one address and an indication of a number of addresses.

20 . The system of claim 16 , wherein the at least one circuit is further configured to perform one or more operations comprising:

receiving an instruction to make the buffer available; and

making the buffer available.