Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices

1 . A processor-based device, comprising:

a translation lookaside buffer (TLB) comprising a plurality of TLB entries, each TLB entry comprising a tag and a plurality of data portions; and

a memory management unit (MMU) configured to:

receive a first memory access request comprising a first virtual address (VA);

determine that a first TLB access to the TLB for a first page VA of the first VA results in a miss; and

responsive to determining that the first TLB access to the TLB for the first page VA of the first VA results in the miss, generate a TLB entry for the first page VA, wherein:

the plurality of data portions comprises a corresponding plurality of page physical addresses (PAs);

a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA;

one or more second data portions of the plurality of data portions comprise corresponding one or more page PAs of corresponding next sequential page VAs following the first page VA; and

the tag of the TLB entry comprises the first page VA and none of the next sequential page VAs following the first page VA.

2 . The processor-based device of claim 1 , wherein each TLB entry of the plurality of TLB entries further comprises a plurality of valid bits that each correspond to a data portion of the plurality of data portions.

3 . The processor-based device of claim 1 , wherein:

each page PA of the plurality of page PAs comprises one of a PA and an intermediate physical address (IPA);

the plurality of page PAs are contiguous in a system memory; and

the MMU is configured to generate the TLB entry for the first page VA by being configured to:

perform an address translation operation to obtain the page PA corresponding to the first page VA;

store the page PA in the first data portion of the TLB entry;

obtain the one or more page PAs of the corresponding next sequential page VAs based on the address translation operation; and

store the one or more page PAs of the corresponding next sequential page VAs in the one or more second data portions of the TLB entry.

4 . The processor-based device of claim 1 , wherein:

each page PA of the plurality of page PAs comprises an intermediate physical address (IPA);

the plurality of page PAs are not contiguous in a system memory; and

the MMU is configured to generate the TLB entry for the first page VA by being configured to:

perform an address translation operation to obtain the page PA corresponding to the first page VA;

store the page PA in the first data portion of the TLB entry;

prefetch an address translation for each of the next sequential page VAs to obtain the one or more page PAs of the corresponding next sequential page VAs; and

update the one or more second data portions of the TLB entry with the one or more page PAs of the corresponding next sequential page VAs.

5 . The processor-based device of claim 1 , wherein the MMU is further configured to:

receive a second memory access request comprising the first VA;

determine that a second TLB access to the TLB for the first page VA of the first VA results in a hit;

responsive to determining that the second TLB access to the TLB for the first page VA of the first VA results in the hit, perform a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry;

receive a third memory access request comprising a second VA;

determine that a second page VA of the second VA corresponds to a next sequential page VA following the first page VA; and

responsive to determining that the second page VA of the second VA corresponds to the next sequential page VA following the first page VA, perform a subsequent memory access operation using the page PA of a second data portion of the one or more second data portions corresponding to the next sequential page VA.

6 . The processor-based device of claim 1 , wherein the tag of the TLB entry further comprises one or more of a context and a page size.

7 . The processor-based device of claim 1 , wherein the plurality of data portions each further comprises one or more memory attributes.

8 . The processor-based device of claim 1 , integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

9 . A processor-based device, comprising:

means for receiving a first memory access request comprising a first virtual address (VA);

means for determining that a first translation lookaside buffer (TLB) access to a TLB of the processor-based device for a first page VA of the first VA results in a miss; and

means for generating a TLB entry for the first page VA responsive to determining that the first TLB access to the TLB for the first page VA of the first VA results in the miss, wherein:

the TLB entry comprises a plurality of data portions that comprises a corresponding plurality of page physical addresses (PAs);

a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA;

one or more second data portions of the plurality of data portions comprise corresponding one or more page PAs of corresponding next sequential page VAs following the first page VA; and

the TLB entry comprises a tag that comprises the first page VA and none of the next sequential page VAs following the first page VA.

10 . A method for exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression, comprising:

receiving, by a memory management unit (MMU) of a processor-based device, a first memory access request comprising a first VA;

determining, by the MMU, that a first TLB access to a TLB of the processor-based device for a first page VA of the first VA results in a miss; and

responsive to determining that the first TLB access to the TLB for the first page VA of the first VA results in the miss, generating, by the MMU, a TLB entry for the first page VA, wherein:

the TLB entry comprises a plurality of data portions that comprises a corresponding plurality of page physical addresses (PAs);

a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA;

one or more second data portions of the plurality of data portions comprise corresponding one or more page PAs of corresponding next sequential page VAs following the first page VA; and

the TLB entry comprises a tag that comprises the first page VA and none of the next sequential page VAs following the first page VA.

11 . The method of claim 10 , wherein each TLB entry of a plurality of TLB entries further comprises a plurality of valid bits that each correspond to a data portion of the plurality of data portions.

12 . The method of claim 10 , wherein:

each page PA of the plurality of page PAs comprises one of a PA and an intermediate physical address (IPA);

the plurality of page PAs are contiguous in a system memory; and

generating the TLB entry for the first page VA comprises:

performing an address translation operation to obtain the page PA corresponding to the first page VA;

storing the page PA in the first data portion of the TLB entry;

obtaining the one or more page PAs of the corresponding next sequential page VAs based on the address translation operation; and

storing the one or more page PAs of the corresponding next sequential page VAs in the one or more second data portions of the TLB entry.

13 . The method of claim 10 , wherein:

each page PA of the plurality of page PAs comprises an intermediate physical address (IPA);

the plurality of page PAs are not contiguous in a system memory; and

generating the TLB entry for the first page VA comprises:

performing an address translation operation to obtain the page PA corresponding to the first page VA;

storing the page PA in the first data portion of the TLB entry;

prefetching an address translation for each of the next sequential page VAs to obtain the one or more page PAs of the corresponding next sequential page VAs; and

updating the one or more second data portions of the TLB entry with the one or more page PAs of the corresponding next sequential page VAs.

14 . The method of claim 10 , further comprising:

receiving, by the MMU, a second memory access request comprising the first VA;

determining, by the MMU, that a second TLB access to the TLB for the first page VA of the first VA results in a hit;

responsive to determining that the second TLB access to the TLB for the first page VA of the first VA results in the hit, performing, by the MMU, a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry;

receiving, by the MMU, a third memory access request comprising a second VA;

determining, by the MMU, that a second page VA of the second VA corresponds to a next sequential page VA following the first page VA; and

responsive to determining that the second page VA of the second VA corresponds to the next sequential page VA following the first page VA, performing, by the MMU, a subsequent memory access operation using the page PA of a second data portion of the one or more second data portions corresponding to the next sequential page VA.

15 . The method of claim 10 , wherein the tag of the TLB entry further comprises one or more of a context and a page size.

16 . The method of claim 10 , wherein the plurality of data portions each further comprises one or more memory attributes.

17 . A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to:

receive a first memory access request comprising a first virtual address (VA);

determine that a first translation lookaside buffer (TLB) access to a TLB of the processor-based device for a first page VA of the first VA results in a miss; and

responsive to determining that the first TLB access to the TLB for the first page VA of the first VA results in the miss, generate a TLB entry for the first page VA, wherein:

the TLB entry comprises a plurality of data portions that comprises a corresponding plurality of page physical addresses (PAS);

a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA;

one or more second data portions of the plurality of data portions comprise corresponding one or more page PAs of corresponding next sequential page VAs following the first page VA; and

the TLB entry comprises a tag that comprises the first page VA and none of the next sequential page VAs following the first page VA.

18 . The non-transitory computer-readable medium of claim 17 , wherein:

each page PA of the plurality of page PAs comprises one of a PA and an intermediate physical address (IPA);

the plurality of page PAs are contiguous in a system memory; and

the computer-executable instructions cause the processor to generate the TLB entry for the first page VA by causing the processor to:

perform an address translation operation to obtain the page PA corresponding to the first page VA;

store the page PA in the first data portion of the TLB entry;

obtain the one or more page PAs of the corresponding next sequential page VAs based on the address translation operation; and

store the one or more page PAs of the corresponding next sequential page VAs in the one or more second data portions of the TLB entry.

19 . The non-transitory computer-readable medium of claim 17 , wherein:

each page PA of the plurality of page PAs comprises one of a PA and an intermediate physical address (IPA);

the plurality of page PAs are not contiguous in a system memory; and

the computer-executable instructions cause the processor to generate the TLB entry for the first page VA by causing the processor to:

perform an address translation operation to obtain the page PA corresponding to the first page VA;

store the page PA in the first data portion of the TLB entry;

prefetch an address translation for each of the next sequential page VAs to obtain the one or more page PAs of the corresponding next sequential page VAs; and

update the one or more second data portions of the TLB entry with the one or more page PAs of the corresponding next sequential page VAs.

20 . The non-transitory computer-readable medium of claim 17 , wherein the computer-executable instructions further cause the processor to:

receive a second memory access request comprising the first VA;

determine that a second TLB access to the TLB for the first page VA of the first VA results in a hit;

responsive to determining that the second TLB access to the TLB for the first page VA of the first VA results in the hit, perform a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry;

receive a third memory access request comprising a second VA;

determine that a second page VA of the second VA corresponds to a next sequential page VA following the first page VA; and

responsive to determining that the second page VA of the second VA corresponds to the next sequential page VA following the first page VA, perform a subsequent memory access operation using the page PA of a second data portion of the one or more second data portions corresponding to the next sequential page VA.