Master-slave switching interface structure of server, and application apparatus thereof
View Patent ↗Embodiments of the present application provide a master-slave switching interface structure of a server. The master-slave switching interface structure includes: at least two input/output interfaces and a routing and switching processor. The routing and switching processor includes: a clock buffer module connected to a first clock input source pin; a local clock module connected to a second clock input source pin; a switch module connected to the first clock input source pin, the first clock output pin, and a clock connection pin. The at least two input/output interfaces are connected to the switch module, and one of the at least two input/output interfaces is a target master-slave switching detection interface; and the routing and switching processor is configured for detecting connection status of the target master-slave switching detection interface, and switching a clock transfer direction of the target master-slave switching detection interface based on the connection status.
1 . A master-slave switching interface structure of a server, wherein the master-slave switching interface structure comprises: at least two input/output interfaces and a routing and switching processor; the routing and switching processor comprises: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module;
the clock buffer module is connected to the first clock input source pin;
the local clock module is connected to the second clock input source pin;
the switch module is connected to the first clock input source pin, the first clock output pin, and the clock connection pin;
the at least two input/output interfaces are connected to the switch module, and one of the at least two input/output interfaces is a target master-slave switching detection interface; and
the routing and switching processor is configured for detecting connection status of the target master-slave switching detection interface, and switching a clock transfer direction of the target master-slave switching detection interface based on the connection status.
2 . The master-slave switching interface structure according to claim 1 , wherein the routing and switching processor further comprises a plurality of general-purpose input/output pins; each of the at least two input/output interfaces comprises a first pin and a second pin; the first pin is disconnected from the second pin; the first pin is connected to one of the plurality of general-purpose input/output pins, and the second pin is grounded.
3 . The master-slave switching interface structure according to claim 2 , wherein each of the at least two input/output interfaces further comprises: a first pull-up resistor; and
one end of the first pull-up resistor is connected to a predetermined power supply, another end of the first pull-up resistor is connected to the first pin and the one of the plurality of general-purpose input/output pins.
4 . The master-slave switching interface structure according to claim 3 , further comprising: cables connected to the at least two input/output interfaces; each of the cables comprises: a third pin and a fourth pin that are short-circuited; in response to the cables being connected to the at least two input/output interfaces, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.
5 . The master-slave switching interface structure according to claim 4 , wherein the routing and switching processor is configured for, in response to detecting a high level, determining that the at least two input/output interfaces are connected to other servers of a cascading server, switching the clock transfer direction of the target master-slave switching detection interface to upstream; in response to detecting a low level, switching the clock transfer direction of the target master-slave switching detection interface to downstream.
6 . The master-slave switching interface structure according to claim 2 , wherein the routing and switching processor is configured for performing port scanning on the plurality of general-purpose input/output pins, and determining the connection status of the target master-slave switching detection interface; in response to the connection status being connected, switching the clock transfer direction of the target master-slave switching detection interface to upstream; in response to the connection status being idle, switching the clock transfer direction of the target master-slave switching detection interface to downstream.
7 . The master-slave switching interface structure according to claim 5 , wherein in response to the clock transfer direction of the target master-slave switching detection interface being downstream, the clock buffer module is connected to the clock connection pin through the switch module; in response to the clock transfer direction of the target master-slave switching detection interface being upstream, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.
8 . The master-slave switching interface structure according to claim 7 , wherein the switch module is a single-pole double-throw switch device;
a first input terminal of the single-pole double-throw switch device is connected to the first clock input source pin;
a second input terminal of the single-pole double-throw switch device is connected to the first clock output pin; and
an output terminal of the single-pole double-throw switch device is connected to the clock connection pin.
9 . The master-slave switching interface structure according to claim 8 , wherein in response to the clock transfer direction of the target master-slave switching detection interface being downstream, the first input terminal of the single-pole double-throw switch device is connected to the output terminal of the single-pole double-throw switch device; in response to the clock transfer direction of the target master-slave switching detection interface being upstream, the second input terminal of the single-pole double-throw switch device is connected to the output terminal of the single-pole double-throw switch device.
10 . The master-slave switching interface structure according to claim 7 , wherein the target master-slave switching detection interface further comprises:
a signal receiving pin; wherein in response to the clock transfer direction of the target master-slave switching detection interface being downstream, the switch module is connected to the clock connection pin, and the signal receiving pin is configured for receiving a signal.
11 . The master-slave switching interface structure according to claim 10 , wherein the signal receiving pin is configured for receiving a clock reset signal, and the clock reset signal is used to reset an output signal of the first clock output pin.
12 . The master-slave switching interface structure according to claim 1 , wherein the master-slave switching interface structure is applied to a computer quick-connect device.
13 . A server connection topology system, comprising a plurality of cascading servers, wherein the plurality of cascading servers are deployed with the master-slave switching interface structure according to claim 1 , and the plurality of cascading servers are interconnected via their respective master-slave switching interface structures.
14 . The server connection topology system according to claim 13 , wherein the plurality of cascading servers are connected by a cable, and the cable comprises:
a plug, connected to the master-slave switching interface structure; and
a second pull-up resistor, connecting a pin of the plug to a predetermined power supply, and configured for placing the pin at a high level.
15 . The server connection topology system according to claim 14 , wherein in response to the cable connected to the master-slave switching interface structure, the master-slave switching interface structure is in a high-level state; in response to the cable being not connected to the master-slave switching interface structure, the master-slave switching interface structure is in a low-level state.
16 . The server connection topology system according to claim 14 , further comprising:
a master-slave switching processor, configured for detecting a level state of the master-slave switching interface structure, and setting the clock transfer direction of the master-slave switching interface structure.
17 . The server connection topology system according to claim 14 , wherein in response to a newly added cascading server existing, a master-slave switching interface structure of the newly added cascading server is connected to the master-slave switching interface structures of other cascading servers by the cable.
18 . A distributed server cluster system, comprising the server connection topology system according to claim 13 .
19 . An electronic device, comprising a processor, a memory, and a computer program stored on the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the master-slave switching interface structure according to claim 1 .
20 . A non-transitory readable storage medium, wherein a computer program is stored on the non-transitory readable storage medium, and the computer program, when executed by a processor, implements the master-slave switching interface structure according to claim 1 .