Credit synchronization by sending a value for a local credit in a message sender from a message receiver to the message sender in response to a synchronization trigger

1 . A storage controller system, comprising:

a first hardware functional module, implemented in hardware on a System On Chip (SOC), that: in response to receiving an indication to re-synchronize a first local credit based at least in part on a first masked credit and independent of a second masked credit associated with a second hardware functional module, sends, to a message sender implemented on the SOC, a first message associated with clearing the first local credit to be a zero value, wherein:

the first local credit is associated with flow control from the message sender to the first hardware functional module; and

the first masked credit is based at least in part on the first local credit and a first re-synchronization register and is independent of a second re-synchronization register associated with the second hardware functional module;

the message sender, implemented on the SOC, that:

in response to receiving the first message from the first hardware functional module, updates the first local credit to be the zero value; and

in the event the message sender has a second message to send to the first hardware functional module:

determines whether the first local credit has a non-zero value or the zero value;

in the event it is determined that the first local credit has the non-zero value, sends the second message to the first hardware functional module; and

in the event it is determined that the first local credit has the zero value, retains the second message; and

a storage interface, implemented on the SOC, that communicates with storage media via an associated channel.

2 . The storage controller system recited in claim 1 , wherein the storage media includes NAND Flash storage media.

3 . The storage controller system recited in claim 1 , wherein the message sender includes firmware associated with the SOC.

4 . The storage controller system recited in claim 1 , further including:

a buffer module; and

a plurality of channel interface modules, wherein each of the plurality of channel interface modules independently acts as a message receiver with the buffer module acting as the message sender.

5 . The storage controller system recited in claim 1 , wherein the first masked credit is an AND combination of the first local credit and the first re-synchronization register.

6 . The storage controller system recited in claim 1 , wherein: in response to detecting that the first hardware functional module has lost synchronization, firmware associated with the SOC writes to the first re-synchronization register, which in turn causes the first masked credit to become a first value associated with clearing the first local credit to be a zero value.

7 . The storage controller system recited in claim 1 , wherein: in response to detecting that the first hardware functional module has lost synchronization, the message sender writes to the first re-synchronization register, which in turn causes the first masked credit to become a first value associated with clearing the first local credit to be a zero value.

8 . The storage controller system recited in claim 1 , wherein:

in response to detecting that the first hardware functional module has lost synchronization, firmware associated with the SOC writes to the first re-synchronization register, which in turn causes the first masked credit to become a first value associated with clearing the first local credit to be a zero value; and

after a new value for the first local credit is determined, the firmware writes to the first re-synchronization register, which in turn causes the first masked credit to become a second value associated with setting the first local credit to be the new value, including by sending, to the message sender, at least one message associated with incrementing the first local credit.

9 . The storage controller system recited in claim 1 , wherein:

in response to detecting that the first hardware functional module has lost synchronization, the message sender writes to the first re-synchronization register, which in turn causes the first local credit to become a value that corresponds to the indication to re-synchronize the first local credit; and

after a new value for the first local credit is determined, the message sender writes to the first re-synchronization register, which in turn causes the first masked credit to become a second value associated with setting the first local credit to be the new value, including by sending, to the message sender, at least one message associated with incrementing the first local credit.

10 . A method for controlling a storage controller system, comprising:

using a first hardware functional module, implemented in hardware on a System On Chip (SOC), to: in response to receiving an indication to re-synchronize a first local credit based at least in part on a first masked credit and independent of a second masked credit associated with a second hardware functional module, send, to a message sender implemented on the SOC, a first message associated with clearing the first local credit to be a zero value, wherein:

the first local credit is associated with flow control from the message sender to the first hardware functional module; and

the first masked credit is based at least in part on the first local credit and a first re-synchronization register and is independent of a second re-synchronization register associated with the second hardware functional module;

using the message sender, implemented on the SOC, to:

in response to receiving the first message from the first hardware functional module, update the first local credit to be the zero value; and

in the event the message sender has a second message to send to the first hardware functional module:

determine whether the first local credit has a non-zero value or the zero value;

in the event it is determined that the first local credit has the non-zero value, send the second message to the first hardware functional module; and

in the event it is determined that the first local credit has the zero value, retain the second message; and

using a storage interface, implemented on the SOC, to communicate with storage media via an associated channel.

11 . The method recited in claim 10 , wherein the storage media includes NAND Flash storage media.

12 . The method recited in claim 10 , wherein the message sender includes firmware associated with the SOC.

13 . The method recited in claim 10 , wherein the storage controller system further includes:

a buffer module; and

a plurality of channel interface modules, wherein each of the plurality of channel interface modules independently acts as a message receiver with the buffer module acting as the message sender.

14 . The method recited in claim 10 , wherein the first masked credit is an AND combination of the first local credit and the first re-synchronization register.

15 . The method recited in claim 10 , wherein: in response to detecting that the first hardware functional module has lost synchronization, firmware associated with the SOC writes to the first re-synchronization register, which in turn causes the first masked credit to become a first value associated with clearing the first local credit to be a zero value.

16 . The method recited in claim 10 , wherein: in response to detecting that the first hardware functional module has lost synchronization, the message sender writes to the first re-synchronization register, which in turn causes the first masked credit to become a first value associated with clearing the first local credit to be a zero value.

17 . The method recited in claim 10 , wherein:

in response to detecting that the first hardware functional module has lost synchronization, firmware associated with the SOC writes to the first re-synchronization register, which in turn causes the first masked credit to become a first value associated with clearing the first local credit to be a zero value; and

after a new value for the first local credit is determined, the firmware writes to the first re-synchronization register, which in turn causes the first masked credit to become a second value associated with setting the first local credit to be the new value, including by sending, to the message sender, at least one message associated with incrementing the first local credit.

18 . The method recited in claim 10 , wherein:

in response to detecting that the first hardware functional module has lost synchronization, the message sender writes to the first re-synchronization register, which in turn causes the first local credit to become a value that corresponds to the indication to re-synchronize the first local credit; and

after a new value for the first local credit is determined, the message sender writes to the first re-synchronization register, which in turn causes the first masked credit to become a second value associated with setting the first local credit to be the new value, including by sending, to the message sender, at least one message associated with incrementing the first local credit.