IP Library Granted Patent US 12693988
Granted Patent B2
US 12693988 · App. 19/146,509 · Granted Jul 28, 2026

Digital power source having adjustable power-on time interval and slew rate, and adjustment method

Inventor: Rengqing Liu (Suzhou, CN)
Assignee: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
G06F13/4068G06F1/26H03K7/08
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Quick Facts
Patent No.
US 12693988
App. No.
19/146,509
Granted
Jul 28, 2026
Kind
B2
Abstract

The present disclosure relates to the technical field of solid state drives, and discloses a digital power supply with adjustable power-on time interval and slew rate and an adjusting method. The digital power supply provides working power for the digital power supply by the power supply circuit, and is integrally controlled by the main control circuit including the main control device and the first interface, and outputs voltage by a multi-channel power supply adjustable circuit including a step-down circuit composed of a first MOS, a second MOS and a filter capacitor, wherein each power supply adjustable circuit corresponds to a power supply rail in the SSD, and in this process, external control parameters are received through the first interface in the main control circuit.

Claims (54)

1 . A digital power supply with adjustable power-on time interval and slew rate, wherein the digital power supply comprises a main control circuit, a power supply circuit and a plurality of power supply adjustable circuits, wherein the main control circuit is respectively connected to the power supply circuit and each power supply adjustable circuit, wherein,

the power supply circuit is configured to provide working power for the digital power supply;

the main control circuit comprises a main control device and a first interface, and is configured to respond to external control parameters received by the first interface, and send pulse-width modulation (PWM) waves to each power adjustable circuit through a first pair of pins of the main control device;

each power supply adjustable circuit comprises a first metal oxide semiconductor (MOS), a second MOS and a filter capacitor, wherein the first MOS, the second MOS and the filter capacitor together form a step-down circuit, and the power supply adjustable circuits are configured to control an on-off of the first MOS and the second MOS in response to the PWM waves of the main control circuit, and output electric energy at a determined power-on time interval and slew rate through the step-down circuit.

2 . The digital power supply according to claim 1 , wherein the main control circuit is further configured to sample a voltage value of each power supply adjustable circuit, and calculate and output PWM waves by digital proportion integration differentiation (PID) based on the voltage value.

3 . The digital power supply according to claim 2 , wherein each power supply adjustable circuit further comprises a feedback resistor and an operational amplifier, wherein the feedback resistor forms a low-pass filter circuit through the operational amplifier, and the low-pass filter circuit is configured to feed back the output voltage value of the corresponding power supply adjustable circuit in response to a voltage sampling requirement of the main control circuit.

4 . The digital power supply according to claim 1 , wherein the main control circuit further comprises a first frequency crystal oscillator and a second frequency crystal oscillator, and the first frequency crystal oscillator and the second frequency crystal oscillator are configured to provide clock signals.

5 . The digital power supply according to claim 1 , wherein the main control circuit further comprises a first indicator light, and the first indicator light is configured to indicate working states of the main control circuit.

6 . The digital power supply according to claim 5 , wherein the first indicator light is configured to have a long bright state and a blinking state, wherein the long bright state is used to indicate that the working state of the main control circuit is a normal state, and the blinking state is used to indicate that the working state of the main control circuit is a fault state.

7 . The digital power supply according to claim 1 , wherein each power supply adjustable circuit further comprises a clamping diode, and the clamping diode is configured to receive an input voltage and protect downstream circuits.

8 . The digital power supply according to claim 1 , wherein each of the power supply adjustable circuits further comprises a second indicator light, and the second indicator is configured to indicate whether the corresponding power supply adjustable circuit has an input voltage.

9 . An adjustment method of a digital power supply with an adjustable power-on time interval and slew rate, applied to the digital power supply according to claim 1 , comprising:

generating a PWM wave corresponding to a power adjustable circuit in response to external control parameters received by a first interface;

based on the PWM wave, controlling an on-off of a first MOS and a second MOS corresponding to the power adjustable circuit;

acquiring a working power supply;

based on the working power supply, outputting electric energy at a determined power-on time interval and slew rate by the on-off of the first MOS and the second MOS.

10 . The method according to claim 9 , wherein generating a PWM wave corresponding to a power adjustable circuit in response to external control parameters received by a first interface comprises:

sampling a voltage value of the corresponding power adjustable circuit;

generating a corresponding PWM wave by digital PID based on the voltage value.

11 . The method according to claim 10 , wherein,

the power supply adjustable circuit comprises a low-pass filter circuit, and the low-pass filter circuit comprises a feedback resistor and an operational amplifier,

the sampling a voltage value of the corresponding power adjustable circuit, comprising:

outputting the voltage value of the corresponding power adjustable circuit by the low-pass filter circuit in the power adjustable circuit, wherein the voltage value is obtained by sampling the power adjustable circuit by the low-pass filter circuit in response to the voltage sampling requirement of the main control circuit.

12 . The method according to claim 10 , wherein,

generating a corresponding PWM wave by digital PID based on the voltage value comprises:

calculating the voltage value by using the digital PID to obtain a target duty ratio of the PWM wave to be output;

generating the PWM wave of the target duty ratio by the main control device.

13 . The method according to claim 9 , wherein, based on the working power supply, outputting electric energy at a determined power-on time interval and slew rate by the on-off of the first MOS and the second MOS comprises:

based on the working power supply, controlling the corresponding power supply adjustable circuit to be powered on at a certain time interval by the on-off of the first MOS and the second MOS;

based on the working power supply, controlling the corresponding power supply adjustable circuit to reach a preset electric energy at a certain time by the on-off of the first MOS and the second MOS.

14 . The method according to claim 13 , wherein, based on the working power supply, controlling the corresponding power supply adjustable circuit to be powered on at a certain time interval by the on-off of the first MOS and the second MOS comprises:

controlling a power-on timing of the corresponding power supply adjustable circuit by the on-off of the first MOS and the second MOS, wherein the power-on timing is used for adjusting a power-on time interval of the power supply adjustable circuit.

15 . The method according to claim 13 , wherein, based on the working power supply, controlling the corresponding power supply adjustable circuit to reach a preset electric energy at a certain time by the on-off of the first MOS and the second MOS comprises:

controlling a target time required for the voltage of the power supply adjustable circuit to reach the output voltage value from 0V by the on-off the first MOS and the second MOS, wherein the target time is used for adjusting a power-on slew rate of the power supply adjustable circuit.

16 . A parallel-operable digital power supply with an adjustable power-on time interval and slew rate, comprising at least two digital power supplies according to claim 1 , wherein,

the main control circuit further comprises a second interface, a third interface and a transfer switch, wherein the transfer switch is configured to indicate an execution priority of each digital power supply; the second interface is configured to transmit external control parameters between at least two digital power supplies; and the third interface is configured to transmit trigger signals between at least two digital power supplies.

17 . The parallel-operable digital power supply according to claim 16 , wherein the third interface is a second pair of pins of the main control device, and the at least two digital power supplies comprise a first digital power supply and a second digital power supply, and the execution priority of the first digital power supply is higher than that of the second digital power supply;

the main control circuit of the first digital power supply is configured to send a trigger signal to the second digital power supply through the second pair of pins of the first digital power supply;

the main control circuit of the second digital power supply is configured to respond to the trigger signal, receive external control parameters through the second interface of the second digital power supply, and send PWM waves to each power supply adjustable circuit corresponding to the second digital power supply through the first pair of pins of the main control device of the second digital power supply.

18 . A parallel-operable adjustment method of a digital power supply with adjustable power-on time interval and slew rate, applied to a first digital power supply in the parallel-operable digital power supply according to claim 16 , wherein the execution priority of the first digital power supply is higher than that of a second digital power supply, comprising:

acquiring a first state of a first transfer switch;

based on the first state, generating a first PWM wave corresponding to the power adjustable circuit in response to the external control parameters received by the first interface;

based on the first PWM wave, controlling an on-off of the first MOS and the second MOS corresponding to the power supply adjustable circuit;

acquiring a first working power supply;

based on the first working power supply, by the on-off of the first MOS and the second MOS, outputting electric energy at a determined power-on time interval and slew rate;

sending the external control parameters to a second digital power supply through a second interface, and sending a trigger signal to the second digital power supply through a third interface.

19 . A parallel-operable adjustment method of a digital power supply with adjustable power-on time interval and slew rate, applied to a second digital power supply in the parallel-operable digital power supply according to claim 16 , wherein the execution priority of thea first digital power supply is higher than that of the second digital power supply, the method comprising:

acquiring a second state of a second transfer switch;

based on the second state, generating a second PWM wave corresponding to the power adjustable circuit by the external control parameters received by the second interface in response to the trigger signal received by the third interface;

based on the second PWM wave, controlling an on-off of a third MOS and a fourth MOS corresponding to the power adjustable circuit;

acquiring a second working power supply;

based on the second working power supply, outputting an electric power at a determined power-on time interval and slew rate by the on-ff of the third MOS and the fourth MOS.

20 . A computer device, comprising:

a memory and a processor, wherein the memory and the processor are in communication connection with each other, and computer instructions are stored in the memory, and the processor executes the computer instructions, to execute the method according to claim 9 .