Verification method and system in artificial neural network array
Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.
1 . A system comprising:
a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents;
a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication array; and
a reference voltage generator to generate one of N voltages during the verify operation, wherein the reference voltage generator comprises:
a current-to-voltage converter for converting a maximum current within the N possible currents into a maximum voltage; and
a resistor string for generating N voltages ranging from the maximum voltage to a minimum voltage, wherein the resistor string comprises (N−1) resistors in series.
2 . The system of claim 1 , wherein the plurality of output blocks converts current from columns of the array into voltages using a plurality of resistors or a plurality of capacitors.
3 . The system of claim 1 comprising:
a verify circuit to compare a voltage from the reference voltage generator with a voltage from one of the plurality of output blocks.
4 . The system of claim 3 , wherein the verify circuit generates a digital output indicating a result of the comparing.
5 . The system of claim 1 , wherein the reference voltage generator generates the one of N voltages in response to a current received from a reference array.
6 . The system of claim 1 , wherein the reference voltage generator generates the one of N voltages in response to a current received from a main reference current generator.
7 . The system of claim 1 , comprising a first buffer for providing the maximum voltage to a first end of the resistor string.
8 . The system of claim 7 , comprising a second buffer for providing the minimum voltage to a second end of the resistor string.
9 . A system comprising:
a current-to-voltage converter to convert a current from a vector-by-matrix array into a voltage;
a successive approximation register analog-to-digital converter to receive the voltage from the current-to-voltage converter and generate a digital output during a read operation; and
a verify circuit to receive the voltage from the current-to-voltage converter and compare it to a reference voltage during a verify operation;
wherein the reference voltage is provided by a reference voltage generator comprising:
a current-to-voltage converter for converting a maximum current within N possible currents into a maximum voltage; and
a resistor string for generating N voltages ranging from the maximum voltage to a minimum voltage, wherein the resistor string comprises (N- 1 ) resistors in series.
10 . The system of claim 9 , comprising a first buffer for providing the maximum voltage to a first end of the resistor string.
11 . The system of claim 10 , comprising a second buffer for providing the minimum voltage to a second end of the resistor string.
12 . A system comprising:
a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents; and
a plurality of reference voltage generators generating K reference voltages on K reference voltage lines, wherein K<N and wherein the K reference voltage lines verify for N possible currents in a time-multiplexed fashion.
13 . The system of claim 12 , comprising:
a plurality of current-to-voltage converters to receive currents from columns of the array of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication array.
14 . The system of claim 13 , wherein the current-to-voltage converter converts current from columns of the array of the vector-by-matrix multiplication array into voltages using a plurality of resistors or a plurality of capacitors.
15 . The system of claim 12 , comprising:
a verify circuit to produce a comparison output.
16 . The system of claim 12 , comprising:
analog-to-digital converters to produce a comparison output.