Watch clocking to improve security of low power processing systems
A processing system including a peripheral configured to store security information and having a clock input receiving a gated clock, a watch clock generator configured to generate a watch clock that has a reduced duty cycle relative to a system clock, and clock control circuitry configured to select the system clock as the gated clock during normal operation of the peripheral and to select the watch clock as the gated clock during a low power mode of the peripheral. The watch clock generator may include a counter that counts system clock cycles and clock pulse selector, such as a modulo circuit, configured to select cycles of the system clock for generating the watch clock. For multiple peripherals, delay circuitry may skew a watch clock between two or more peripherals. Multiple watch clocks with different delayed duty cycles may be generated, each for a corresponding one of multiple groups of peripherals.
1 . A processing system, comprising:
a peripheral configured to store security information and having a clock input receiving a gated clock;
a watch clock generator configured to generate a watch clock that has a reduced duty cycle relative to a system clock; and
clock control circuitry configured to select the system clock as the gated clock during normal operation of the peripheral and to select the watch clock as the gated clock during a low power mode of the peripheral,
wherein the watch clock generator comprises:
a counter configured to count cycles of the system clock and to provide a count value indicative thereof; and
a clock pulse selector comprises modulo circuitry configured to provide a pulse on the watch clock whenever the count value divided by 2 M equals zero in which M is a watch clock factor.
2 . The processing system of claim 1 , wherein the clock pulse selector is configured to provide the pulse on the watch clock for every 2 M pulses of the system clock.
3 . The processing system of claim 1 , wherein the clock control circuitry is configured to select the system clock as the gated clock when the system clock enabled and to select the watch clock as the gated clock when the watch clock is enabled while the system clock is disabled.
4 . The processing system of claim 1 , wherein the clock control circuitry is configured to select the system clock as the gated clock when the system clock is enabled or while a clock request signal from the peripheral is asserted and that selects the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled and when the clock request signal from the peripheral is negated.
5 . The processing system of claim 1 , further comprising:
a second peripheral configured to store security information and having a clock input receiving a second gated clock;
delay circuitry configured to delay the watch clock and to provide a delayed watch clock; and
wherein the clock control circuitry is configured to select the system clock as the second gated clock during normal operation of the second peripheral and to select the delayed watch clock as the second gated clock during a low power mode of the second peripheral.
6 . The processing system of claim 5 , wherein the delay circuitry comprises a shift register.
7 . The processing system of claim 1 , further comprising:
the peripheral comprising one of a plurality of peripherals each configured to store security information and each having a clock input receiving a corresponding one of a plurality of gated clocks;
delay circuitry configured to delay the watch clock and to provide a plurality of delayed watch clocks each skewed relative to each other; and
wherein the clock control circuitry is configured to select the system clock as the gated clock of a corresponding one of the plurality of peripherals during normal operation of the corresponding peripheral and to select a corresponding one of the plurality of delayed watch clocks as the gated clock during a low power mode of the corresponding peripheral.
8 . The processing system of claim 1 , further comprising:
the peripheral comprising one of a plurality of peripherals each configured to store security information and each having a clock input receiving a corresponding one of a plurality of gated clocks, wherein the plurality of peripherals are subdivided into a plurality of groups;
wherein the watch clock generator comprises one of a plurality of watch clock generators each configured to generate a corresponding one of a plurality of primary watch clocks each having a corresponding one of a plurality of different reduced duty cycles relative to the system clock, wherein each of the plurality of watch clock generators generates a corresponding primary watch clock for a corresponding one of the plurality of groups;
delay circuitry configured to delay each of the plurality of primary watch clocks and to provide a plurality of delayed watch clocks that are skewed relative to each other for each of the plurality of groups; and
wherein the clock control circuitry is configured to select the system clock as the gated clock of a corresponding one of the plurality of peripherals during normal operation of the corresponding peripheral and to select a corresponding one of the plurality of primary watch clocks or a corresponding one of the plurality delay watch clocks as the gated clock during a low power mode of the corresponding peripheral.
9 . A method, comprising:
in a processing system comprising a peripheral configured to store security information and having a clock input receiving a gated clock:
generating a watch clock that has a reduced duty cycle relative to a system clock; and
selecting the system clock as the gated clock during normal operation of the peripheral and selecting the watch clock as the gated clock during a low power mode of the peripheral,
wherein the generating the watch clock comprises:
counting cycles of the system clock and providing a count value indicative thereof; and
providing a pulse on the watch clock whenever the count value divided by 2 M equals zero in which Mis a watch clock factor.
10 . The method of claim 9 , wherein the providing comprises providing the pulse on the watch clock for every 2 M pulses of the system clock.
11 . The method of claim 9 , wherein the selecting comprises selecting the system clock as the gated clock when the system clock is enabled and selecting the watch clock as the gated clock when the watch clock is enabled while the system clock is disabled.
12 . The method of claim 9 , wherein the selecting comprises selecting the system clock as the gated clock when the system clock is enabled or while a clock request signal from the peripheral is asserted and selecting the watch clock as the gated clock when the watch clock is enabled and the system clock is disabled and when the clock request signal from the peripheral is negated.
13 . The method of claim 9 , wherein the processing system comprises a second peripheral configured to store security information and having a clock input for receiving a second gated clock, further comprising:
delaying the watch clock and providing a delayed watch clock; and
selecting the system clock as the second gated clock during normal operation of the second peripheral and selecting the delayed watch clock as the second gated clock during a low power mode of the second peripheral.
14 . The method of claim 13 , wherein the delaying comprises shifting the watch clock through a shift register clocked by the system clock and providing at least one delayed watch clock.
15 . The method of claim 9 , wherein the peripheral comprises one of a plurality of peripherals each configured to store security information and each having a clock input receiving a corresponding one of a plurality of gated clocks, the method further comprising:
delaying the watch clock and providing a plurality of delayed watch clocks each skewed relative to each other; and
selecting the system clock as the gated clock of a corresponding one of the plurality of peripherals during normal operation of the corresponding peripheral and selecting a corresponding one of the plurality of delayed watch clocks as the gated clock during a low power mode of the corresponding peripheral.
16 . The method of claim 9 , wherein the peripheral comprises one of a plurality of peripherals each configured to store security information and each having a clock input receiving a corresponding one of a plurality of gated clocks, and wherein the plurality of peripherals are subdivided into a plurality of groups, the method further comprising:
generating a corresponding one of a plurality of primary watch clocks for each of the plurality of groups, each of the plurality of primary watch clocks having a corresponding one of a plurality of different reduced duty cycles relative to the system clock;
delaying each of the plurality of primary watch clocks and providing a plurality of delayed watch clocks that are skewed relative to each other for each of the plurality of groups; and
selecting the system clock as the gated clock of a corresponding one of the plurality of peripherals during normal operation of the corresponding peripheral and selecting a corresponding one of the plurality of primary watch clocks or a corresponding one of the plurality delay watch clocks as the gated clock during a low power mode of the corresponding peripheral.