Terminal chip and measurement method thereof

1 . A terminal chip comprising a computing subsystem and a security subsystem, wherein the security subsystem is configured to measure the computing subsystem, a boot time of the security subsystem is earlier than a boot time of the computing subsystem, the security subsystem comprises:

an integrity verification unit configured to perform integrity measurement on data in a boot process of the computing subsystem;

a shared buffer comprised in an on-chip memory configured for communication between the computing subsystem and the security subsystem; and

a filter configured to intercept a first access operation of the computing subsystem, wherein the first access operation is used to request to access resources other than the shared buffer in the security subsystem.

2 . The terminal chip according to claim 1 , wherein the security subsystem further comprises: a first interaction interface, and the security subsystem accesses resources of the computing subsystem through the first interaction interface.

3 . The terminal chip according to claim 1 , wherein the integrity verification unit is further configured to perform integrity measurement on data in a running process of the computing subsystem.

4 . The terminal chip according to claim 3 , wherein the integrity verification unit is specifically configured to perform integrity measurement on the data during running of the computing subsystem in response to that the computing subsystem is switched from a rich execution environment REE to a trusted execution environment TEE.

5 . The terminal chip according to claim 3 , wherein the security subsystem further comprises: a timer, wherein the timer is configured to perform timing; and

the integrity verification unit is specifically further configured to periodically perform integrity measurement on the data during running of the computing subsystem based on the timer.

6 . The terminal chip according to claim 1 , wherein the filter is further configured to intercept a second access operation of the security subsystem, wherein the second access operation is used to request to write data into the computing subsystem.

7 . The terminal chip according to claim 1 , wherein the security subsystem further comprises: a read-only memory (ROM) and a processor, wherein

the ROM is configured to store a computer program when the security subsystem is powered on; and

the processor is configured to run the computer program stored in the ROM.

8 . The terminal chip according to claim 1 , wherein the security subsystem further comprises a crypto engine, wherein

the crypto engine is configured to provide a cryptographic algorithm; and

the integrity verification unit is specifically configured to invoke the cryptographic algorithm provided by the crypto engine and perform integrity measurement on the data in the boot process and data in a running process of the computing subsystem.

9 . The terminal chip according to claim 1 , wherein the security subsystem comprises a power supply clock management unit, and the power supply clock management unit is configured to perform power-on or power-off control on the security subsystem.

10 . A method for a terminal chip, wherein the terminal chip comprises a computing subsystem and a security subsystem, and the method comprises:

powering on and booting the security subsystem, wherein the security subsystem is configured to measure the computing subsystem, and the security subsystem comprises a shared buffer comprised in an on-chip memory configured for communication between the computing subsystem and the security subsystem;

powering on and booting the computing subsystem after the security subsystem is booted;

performing, by the security subsystem, integrity measurement on data in a boot process of the computing subsystem; and

intercepting, by the security subsystem, a first access operation of the computing subsystem, wherein the first access operation is used to access resources other than the shared buffer in the security subsystem.

11 . The method according to claim 10 , wherein the method further comprises:

performing, by the security subsystem, integrity measurement on data in a running process of the computing subsystem.

12 . The method according to claim 11 , wherein the performing, by the security subsystem, integrity measurement on data in a running process of the computing subsystem comprises:

performing, by the security subsystem, integrity measurement on the data during running of the computing subsystem in response to that the computing subsystem is switched from a rich execution environment REE to a trusted execution environment TEE.

13 . The method according to claim 11 , wherein the performing, by the security subsystem, integrity measurement on data in a running process of the computing subsystem comprises:

periodically performing, by the security subsystem, integrity measurement on the data in the running process of the computing subsystem.

14 . The method according to claim 10 , wherein the performing, by the security subsystem, integrity measurement on data in a boot process of the computing subsystem comprises:

calculating, by the security subsystem, a feature value of the data in the boot process of the computing subsystem, and comparing the feature value with a reference value, to indicate whether the computing subsystem is attacked.

15 . The method according to claim 14 , wherein in response to determining that the feature value is the same as the reference value, the method further comprises:

sending, by the security subsystem, a first indication signal to the computing subsystem, wherein the first indication signal indicates that the computing subsystem is not attacked.

16 . The method according to claim 14 , wherein in response to determining that the feature value is different from the reference value, the method further comprises:

sending, by the security subsystem, indication information to a server, wherein the indication information indicates that the computing subsystem is attacked; or

sending, by the security subsystem, a second indication signal to the computing subsystem, wherein the second indication signal is used to reset the computing subsystem.

17 . The method according to claim 10 , wherein the method further comprises:

sending, by the security subsystem, a third indication signal to an external power supply management unit, wherein the third indication signal indicates the external power supply management unit to perform power-on or power-off control on the security subsystem.

18 . The method according to claim 10 , wherein the method further comprises:

intercepting, by the security subsystem, a second access operation of the security subsystem, wherein the second access operation is used to request to write data into the computing subsystem.

19 . The method according to claim 10 , wherein the security subsystem comprises a read-only memory (ROM) and a processor, and wherein powering on and booting the security subsystem comprises:

running, by the processor, a computer program stored in the ROM.

20 . The method according to claim 10 , wherein the security subsystem comprises a crypto engine configured to provide a cryptographic algorithm, and wherein performing the integrity measurement comprises:

invoking, by the security subsystem, the cryptographic algorithm provided by the crypto engine to perform the integrity measurement on the data in the boot process.