High-level-synthesis for RISC-V system-on-chip generation for field programmable gate arrays
An article of manufacture includes a medium with instructions that when read and executed by a processor, cause the processor to identify a code stream to be executed by a system-on-a-chip (SoC). The SoC is to include an open standard processor and hardware accelerators implemented in reprogrammable hardware. The processor is to, from the code stream, identify a first portion of the code stream to be executed as software by the open standard processor and a second portion to be executed in the accelerators, compile the first portion into a binary for execution by the open standard processor, and generate a hardware description for the second portion to be implemented by the hardware accelerators. The hardware description and the binary are to exchange data during execution of the code stream.
1 . An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, cause the processor to:
identify a code stream to be executed by a system-on-a-chip (SoC), the SoC to include an open standard instruction set architecture (ISA) processor and one or more hardware accelerators implemented in reprogrammable hardware;
from the code stream, identify a first portion of the code stream to be executed as software by the open standard ISA processor of the SoC and a second portion of the code stream to be executed in the one or more hardware accelerators of the SoC;
compile the first portion of the code stream into a binary for execution by the open standard ISA processor of the SoC;
generate a hardware description for the second portion of the code stream to be implemented by the one or more hardware accelerators; and
wherein the hardware description and the binary are to exchange data during execution of the code stream.
2 . The article of claim 1 , wherein the processor is to selectively generate the binary for the open standard ISA processor as implemented as a hardened processor in the SoC or the open standard ISA processor as implemented as a soft processor in the reprogrammable hardware of the SoC.
3 . The article of claim 1 , wherein the processor is to selectively generate a hardware architecture of the hardware description based upon a user-specified transmission method of exchanging data between the hardware description and the binary.
4 . The article of claim 1 , wherein the processor is to generate the binary to allocate a contiguous block of memory for use by the open standard ISA processor, based upon a contiguous allocation command in the code stream.
5 . The article of claim 1 , wherein the processor is to, based upon a first transfer instruction in the code stream, generate the hardware description and compile the binary to cause the open standard ISA processor and a first hardware accelerator of the one or more hardware accelerators to exchange data during execution of the code stream through a buffer in the reprogrammable hardware with a direct memory access core.
6 . The article of claim 1 , wherein the processor is to, based upon a second transfer instruction in the code stream, generate the hardware description and compile the binary to cause the open standard ISA processor and a first hardware accelerator to exchange data during execution of the code stream through a buffer in the reprogrammable hardware without direct memory access.
7 . The article of claim 1 , wherein the processor is to, based upon a third transfer instruction in the code stream, generate the hardware description and compile the binary to cause the open standard ISA processor and a first hardware accelerator to exchange data during execution of the code stream directly through a bypass of a buffer in the reprogrammable hardware.
8 . A method, comprising:
identifying a code stream to be executed by a system-on-a-chip (SoC), the SoC to include an open standard ISA processor and one or more hardware accelerators implemented in reprogrammable hardware;
from the code stream, identifying a first portion of the code stream to be executed as software by the open standard ISA processor of the SoC and a second portion of the code stream to be executed in the one or more hardware accelerators of the SoC;
compiling the first portion of the code stream into a binary for execution by the open standard ISA processor of the SoC;
loading the binary onto the SoC;
generating a hardware description for the second portion of the code stream to be implemented by the one or more hardware accelerators; and
loading the hardware description onto the SoC;
wherein the hardware description and the binary are to exchange data during execution of the code stream.
9 . The method of claim 8 , comprising selectively generating the binary for the open standard ISA processor as implemented as a hardened processor in the SoC or open standard ISA processor as implemented as a soft processor in the reprogrammable hardware of the SoC.
10 . The method of claim 8 , comprising selectively generating a hardware architecture of the hardware description based upon a user-specified transmission method of exchanging data between the hardware description and the binary.
11 . The method of claim 8 , comprising generating the binary to allocate a contiguous block of memory for use by the open standard ISA processor, based upon a contiguous allocation command in the code stream.
12 . The method of claim 8 , comprising, based upon a first transfer instruction in the code stream, generating the hardware description and compile the binary to cause the open standard ISA processor and a first hardware accelerator to exchange data during execution of the code stream through a buffer in the reprogrammable hardware with a direct memory access core.
13 . The method of claim 8 , comprising, based upon a second transfer instruction in the code stream, generating the hardware description and compile the binary to cause the open standard ISA processor and a first hardware accelerator to exchange data during execution of the code stream through a buffer in the reprogrammable hardware without director memory access.
14 . The method of claim 8 , comprising, based upon a third transfer instruction in the code stream, generating the hardware description and compile the binary to cause the open standard ISA processor and a first hardware accelerator to exchange data during execution of the code stream directly through a bypass of a buffer in the reprogrammable hardware.
15 . A system-on-a-chip (SoC), comprising:
an open standard ISA processor;
one or more hardware accelerators implemented in reprogrammable hardware;
wherein the open standard ISA processor is to execute a binary generated from a first portion of a code stream;
a second portion of the code stream is to be implemented by a hardware description in the one or more hardware accelerators;
wherein the hardware description and the binary are to exchange data during execution of the code stream.
16 . The SoC of claim 15 , wherein the open standard ISA processor is implemented as a soft processor in the reprogrammable hardware of the SoC.
17 . The SoC of claim 15 , wherein the binary is to allocate a contiguous block of memory for use by the open standard ISA processor based upon a contiguous allocation command in the code stream.
18 . The SoC of claim 15 , wherein the open standard ISA processor and one of the hardware accelerators are to, based upon a first transfer instruction in the code stream, exchange data during execution of the code stream through a buffer in the reprogrammable hardware with a direct memory access core.
19 . The SoC of claim 15 , wherein the open standard ISA processor and one of the hardware accelerators are to, based upon a second transfer instruction in the code stream, exchange data during execution of the code stream through a buffer in the reprogrammable hardware without director memory access.
20 . The SoC of claim 15 , wherein the open standard ISA processor and one of the hardware accelerators are to, based upon a third transfer instruction in the code stream, exchange data during execution of the code stream directly through a bypass of a buffer in the reprogrammable hardware.