Modifying the topology of circuits containing mixed signal subcircuits to enable electro-optical co-simulation
A method of simulating a mixed-signal circuit design, includes, dividing a first circuit disposed in a first level of hierarchy of the circuit design into a multitude of subcircuits. At least a first subcircuit processes an electrical signal, and at a least a second subcircuit processes an optical signal; adding one or more input/output terminals to the first subcircuit to transform the subcircuit into a first subblock; adding one or more input/output terminals to the second subcircuit to transform the second subcircuit into a second subblock; replacing an instance of the first circuit design in a second level of hierarchy of the mixed-signal design with the first and second subblocks; simulating the first subblock in each of the first and second levels of the hierarchy using an electrical circuit simulator; and simulating the second subblock in each of the first and second levels of the hierarchy using an optical simulator.
1 . A method of simulating a mixed-signal circuit design, the method comprising:
dividing a first circuit design disposed in a first level of hierarchy of the mixed-signal circuit design into a plurality of subcircuits, wherein at least a first one of the plurality of subcircuits is adapted to process an electrical signal, and at a least a second one of the plurality of subcircuits is adapted to process an optical signal;
adding one or more input/output terminals to the first one of the plurality of subcircuits to transform the first one of the plurality of subcircuits into a first subblock;
adding one or more input/output terminals to the second one of the plurality of subcircuits to transform the second one of the plurality of subcircuits into a second subblock;
replacing, by a processing device, an instance of the first circuit design in a second level of hierarchy of the mixed-signal circuit design with the first and second subblocks;
performing a simulation of the first subblock associated with each of the first and second levels of the hierarchy using an electrical circuit simulator; and
performing a simulation of the second subblock associated with each of the first and second levels of the hierarchy using an optical circuit simulator.
2 . The method of claim 1 wherein at least a third one of the plurality of subcircuits of the first level of hierarchy is adapted to process an optical signal, the method further comprising:
disposing the third one of the plurality of subcircuits in the second subblock of the first level of hierarchy.
3 . The method of claim 1 wherein the first one of the plurality of subcircuits is adapted to process an analog electrical signal, the method further comprising:
performing the simulation of the first subblock associated with each of the first and second levels of the hierarchy using an analog circuit simulator.
4 . The method of claim 1 wherein the first one of the plurality of subcircuits is adapted to process a digital electrical signal, the method further comprising:
performing the simulation of the first subblock associated with each of the first and second levels of the hierarchy using a digital circuit simulator.
5 . The method of claim 1 wherein the first one of the plurality of subcircuits is adapted to process an analog electrical signal, and wherein a third one of the plurality of subcircuits is adapted to process a digital electrical signal, the method comprising:
adding one or more input/output terminals to the third one of the plurality of subcircuits to transform the third one of the plurality of subcircuits into a third subblock;
replacing an instance of the first circuit design in a third level of hierarchy of the mixed-signal circuit design with the first, second and third subblocks;
performing a simulation of the first subblock associated with each of the first and third levels of the hierarchy using an analog circuit simulator;
performing a simulation of the second subblock associated with each of the first and third levels of the hierarchy using an optical circuit simulator; and
performing a simulation of the third subblock in each of the first and third levels of the hierarchy using a digital circuit simulator.
6 . The method of claim 1 further comprising:
traversing through the hierarchy of the mixed-signal circuit design in a descending order to perform the replacing.
7 . The method of claim 1 wherein the first level of hierarchy is a highest level of the hierarchy of the mixed-signal circuit design.
8 . A system for simulating a mixed-signal circuit design comprising, the system comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
divide a first circuit design disposed in a first level of hierarchy of the mixed-signal circuit design into a plurality of subcircuits, wherein at least a first one of the plurality of subcircuits is adapted to process an electrical signal, and at a least a second one of the plurality of subcircuits is adapted to process an optical signal;
add one or more input/output terminals to the first one of the plurality of subcircuits to transform the first one of the plurality of subcircuits into a first subblock;
add one or more input/output terminals to the second one of the plurality of subcircuits to transform the second one of the plurality of subcircuits into a second subblock;
replace an instance of the first circuit design in a second level of hierarchy of the mixed-signal circuit design with the first and second subblocks;
perform a simulation of the first subblock associated with each of the first and second levels of the hierarchy using an electrical circuit simulator; and
perform a simulation of the second subblock associated with each of the first and second levels of the hierarchy using an optical circuit simulator.
9 . The system of claim 8 wherein at least a third one of the plurality of subcircuits of the first level of hierarchy is adapted to process an optical signal, wherein the instructions further cause the processor to:
dispose the third one of the plurality of subcircuits in the second subblock of the first level of hierarchy.
10 . The system of claim 8 wherein the first one of the plurality of subcircuits is adapted to process an analog electrical signal, wherein the instructions further cause the processor to:
perform the simulation of the first subblock associated with each of the first and second levels of the hierarchy using an analog circuit simulator.
11 . The system of claim 8 wherein the first one of the plurality of subcircuits is adapted to process a digital electrical signal, wherein the instructions further cause the processor to:
perform the simulation of the first subblock associated with each of the first and second levels of the hierarchy using a digital circuit simulator.
12 . The system of claim 8 wherein the first one of the plurality of subcircuits is adapted to process an analog electrical signal, and wherein a third one of the plurality of subcircuits is adapted to process a digital electrical signal, wherein the instructions further cause the processor to:
add one or more input/output terminal to the third one of the plurality of subcircuits to transform the third one of the plurality of subcircuits into a third subblock;
replace an instance of the first circuit design in a third level of hierarchy of the mixed-signal circuit design with the first, second and third subblocks;
perform a simulation of the first subblock associated with each of the first and third levels of the hierarchy using an analog circuit simulator;
perform a simulation of the second subblock associated with each of the first and third levels of the hierarchy using an optical circuit simulator; and
perform a simulation of the third subblock in each of the first and third levels of the hierarchy using a digital circuit simulator.
13 . The system of claim 8 , wherein the instructions further cause the processor to:
traverse through the hierarchy of the mixed-signal circuit design in a descending order to perform the replacement.
14 . The system of claim 8 wherein the first level of hierarchy is a highest level of the hierarchy of the mixed-signal circuit design.
15 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
divide a first circuit design disposed in a first level of hierarchy of the mixed-signal circuit design into a plurality of subcircuits, wherein at least a first one of the plurality of subcircuits is adapted to process an electrical signal, and at a least a second one of the plurality of subcircuits is adapted to process an optical signal;
add one or more input/output terminals to the first one of the plurality of subcircuits to transform the first one of the plurality of subcircuits into a first subblock;
add one or more input/output terminals to the second one of the plurality of subcircuits to transform the second one of the plurality of subcircuits into a second subblock;
replace an instance of the first circuit design in a second level of hierarchy of the mixed-signal circuit design with the first and second subblocks;
perform a simulation of the first subblock associated with each of the first and second levels of the hierarchy using an electrical circuit simulator; and
perform a simulation of the second subblock associated with each of the first and second levels of the hierarchy using an optical circuit simulator.
16 . The non-transitory computer readable medium 15 wherein at least a third one of the plurality of subcircuits of the first level of hierarchy is adapted to process an optical signal, wherein the instructions further cause the processor to:
dispose the third one of the plurality of subcircuits in the second subblock of the first level of hierarchy.
17 . The non-transitory computer readable medium 15 wherein the first one of the plurality of subcircuits is adapted to process an analog electrical signal, wherein the instructions further cause the processor to:
perform the simulation of the first subblock associated with each of the first and second levels of the hierarchy using an analog circuit simulator.
18 . The non-transitory computer readable medium 15 wherein the first one of the plurality of subcircuits is adapted to process a digital electrical signal, wherein the instructions further cause the processor to:
perform the simulation of the first subblock associated with each of the first and second levels of the hierarchy using a digital circuit simulator.
19 . The non-transitory computer readable medium 15 wherein the first one of the plurality of subcircuits is adapted to process an analog electrical signal, and wherein a third one of the plurality of subcircuits is adapted to process a digital electrical signal, wherein the instructions further cause the processor to:
add one or more input/output terminal to the third one of the plurality of subcircuits to transform the third one of the plurality of subcircuits into a third subblock;
replace an instance of the first circuit design in a third level of hierarchy of the mixed-signal circuit design with the first, second and third subblocks;
perform a simulation of the first subblock associated with each of the first and third levels of the hierarchy using an analog circuit simulator;
perform a simulation of the second subblock associated with each of the first and third levels of the hierarchy using an optical circuit simulator; and
perform a simulation of the third subblock in each of the first and third levels of the hierarchy using a digital circuit simulator.
20 . The non-transitory computer readable medium 15 , wherein the instructions further cause the processor to:
traverse through the hierarchy of the mixed-signal circuit design in a descending order to perform the replacement.