Method of shuttle mask

1 . A design method of a shuttle mask, comprising:

providing a first integrated circuit (IC) design in a first chip region and providing a second IC design in a second chip region, wherein the first IC design includes first main patterns, and the second IC design includes second main patterns;

adding first dummy insertion patterns in the first chip region and adding second dummy insertion patterns in the second chip region; and

after adding the first dummy insertion patterns in the first chip region and adding the second dummy insertion patterns in the second chip region, determining whether the number of layers of a first back end of line (BEOL) structure of the first IC design is the same as the number of layers of a second BEOL structure of the second IC design, wherein

the first main patterns and the first dummy insertion patterns are separated from each other,

the first dummy insertion patterns are patterns formed by duplicating at least one of the first main patterns,

the second main patterns and the second dummy insertion patterns are separated from each other, and

the second dummy insertion patterns are patterns formed by duplicating at least one of the second main patterns.

2 . The design method of the shuttle mask according to claim 1 , wherein a method of adding the first dummy insertion patterns in the first chip region comprises randomly adding the first dummy insertion patterns in the first chip region.

3 . The design method of the shuttle mask according to claim 1 , wherein a method of adding the second dummy insertion patterns in the second chip region comprises randomly adding the second dummy insertion patterns in the second chip region.

4 . The design method of the shuttle mask according to claim 1 , further comprising:

ending a design process of the shuttle mask when the number of layers of the first BEOL structure of the first IC design is not the same as the number of layers of the second BEOL structure of the second IC design.

5 . The design method of the shuttle mask according to claim 1 , further comprising:

adding at least one dummy line in the second chip region when the number of layers of the first BEOL structure of the first IC design is the same as the number of layers of the second BEOL structure of the second IC design, wherein

the at least one dummy line is connected to at least two selected from the second main patterns and the second dummy insertion patterns.

6 . The design method of the shuttle mask according to claim 5 , further comprising:

after adding the at least one dummy line in the second chip region, ending a design process of the shuttle mask.

7 . The design method of the shuttle mask according to claim 5 , wherein a method of adding the at least one dummy line in the second chip region comprises randomly adding the at least one dummy line in the second chip region.

8 . The design method of the shuttle mask according to claim 5 , wherein the at least one dummy line has a first side and a second side, the second side is located between the first side and a center of the second chip region, and the number of the second dummy insertion patterns connected to the first side is two or more.

9 . The design method of the shuttle mask according to claim 5 , wherein the at least one dummy line has a first side and a second side, the second side is located between the first side and a center of the second chip region, and the number of the second dummy insertion patterns connected to the second side is less than two.

10 . The design method of the shuttle mask according to claim 5 , wherein the at least one dummy line has a first side and a second side, the second side is located between the first side and a center of the second chip region, and the number of the second dummy insertion patterns connected to the first side is less than two.

11 . The design method of the shuttle mask according to claim 5 , wherein the at least one dummy line has a first side and a second side, the second side is located between the first side and a center of the second chip region, and the number of the second dummy insertion patterns connected to the second side is two or more.

12 . The design method of the shuttle mask according to claim 1 , wherein two or more of the first main patterns have different shapes.

13 . The design method of the shuttle mask according to claim 1 , wherein two or more of the first main patterns have the same shape.

14 . The design method of the shuttle mask according to claim 1 , wherein two or more of the second main patterns have different shapes.

15 . The design method of the shuttle mask according to claim 1 , wherein two or more of the second main patterns have the same shape.

16 . The design method of the shuttle mask according to claim 1 , wherein two or more of the first dummy insertion patterns have different shapes.

17 . The design method of the shuttle mask according to claim 1 , wherein two or more of the first dummy insertion patterns have the same shape.

18 . The design method of the shuttle mask according to claim 1 , wherein two or more of the second dummy insertion patterns have different shapes.

19 . The design method of the shuttle mask according to claim 1 , wherein two or more of the second dummy insertion patterns have the same shape.