IP Library Granted Patent US 12694192
Granted Patent B1
US 12694192 · App. 19/314,187 · Granted Jul 28, 2026

Use of AI image generation model to create high-level visualization of a network-on-chip

Inventors: Ugo Lecerf (Paris, FR); Donatello Conte (Paris, FR); Pierre-Henri Bonnaud (Sophia Antipolis, FR)
Assignee: ARTERIS, INC.
G06F30/392G06F30/27G06N3/0499G06F2115/02
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Quick Facts
Patent No.
US 12694192
App. No.
19/314,187
Granted
Jul 28, 2026
Kind
B1
Abstract

An image of a floorplan of an electronic system is accessed. The floorplan shows blockages, free space and connection ports for a Network-on-Chip (NoC). The image is supplied as an input to an AI image generation model that has been trained to add NoC switches at probable positions in the free space of the floorplan in view of the connection ports. An output of the AI image generation model provides a high-level visualization of a NoC architecture.

Claims (25)

1 . A computer-aided design method comprising:

accessing an image, which is at least one of: black and white image, a grayscale image, and a color image, of a floorplan of an electronic system, the floorplan including:

blockages;

free space; and

connection ports for a Network-on-Chip (NoC); and

supplying the image as an input to an AI image generation model that has been trained to add NoC switches at probable positions in the free space of the image in view of the connection ports, wherein an output of the AI image generation model provides a high-level visualization of a NoC architecture including placement of switches in the free space identified in the image and free of wire connections between the NoC switches.

2 . The computer-aided design method of claim 1 , wherein the AI image generation model is further trained to color-code the NoC switches.

3 . The computer-aided design method of claim 1 , further comprising color-coding the blockages and the connection ports in the image prior.

4 . The computer-aided design method of claim 1 , wherein the AI image generation model has been further trained to add NoC adapters to the free space; and wherein the high-level visualization also includes NoC adapters in the free space.

5 . The computer-aided design method of claim 1 , wherein the AI image generation model is a stable diffusion model.

6 . The computer-aided design method of claim 1 , further comprising extracting coordinates of the NoC switches in the high-level visualization; and creating a list of the coordinates.

7 . The computer-aided design method of claim 1 , further comprising supplying text description of the floorplan to the AI image generation model.

8 . The computer-aided design method of claim 1 , further comprising iteratively generating a topology of the NoC, using the high-level visualization as a starting point.

9 . The computer-aided design method of claim 8 , wherein iteratively generating the topology of the NoC includes creating an initial iteration, wherein creating the initial iteration includes searching for a routing between the connection ports in the NoC architecture using the NoC switches at probable locations in the free space.

10 . The computer-aided design method of claim 9 , wherein the searching is performed by an algorithm that uses the NoC switches at the probable locations as candidates.

11 . The computer-aided design method of claim 1 , wherein the AI image generation model was trained with images of switches in well designed NoC topologies.

12 . An electronic computer aided design (ECAD) tool comprising a non-transitory computer readable medium encoded with code, that when executed by one or more processors, causes the ECAD tool to:

access an image of a floorplan of an electronic system, wherein the image is at least one of black and white image, a greyscale image, and a color image and wherein the image including at least one or more of:

blockages;

free space; and

connection ports for a Network-on-Chip (NoC); and

supply the image as an input to an AI image generation model that has been trained to add NoC switches, which are represented visually in the image of the floorplan, at probable positions in the free space while avoiding position within the blockages, wherein an output of an AI image generation model provides a high-level visualization of the NoC and the output includes placement of switches in free space located in the image and free of wire connections between the NOC switches.

13 . The ECAD tool of claim 12 , wherein the code, when executed, further causes the ECAD tool to extract coordinates of the NoC switches in the high-level visualization; and create a list of the coordinates.

14 . The ECAD tool of claim 12 , wherein the AI image generation model is a stable diffusion model.

15 . The ECAD tool of claim 12 , wherein the code, when executed, further causes the ECAD tool to iteratively generate a topology of the NoC, using the high-level visualization as a starting point.