Application negotiable platform thermal aware scheduler
An embodiment of an integrated circuit may comprise a management controller and circuitry communicatively coupled to the management controller, the circuitry to dynamically determine a performance measurement for each of two or more circuit blocks based at least in part on the physical design layout of the two or more circuit blocks, and report a schedule recommendation to an operating system scheduler based at least in part on the determined performance measurements. Other embodiments are disclosed and claimed.
1 . An integrated circuit, comprising:
a management controller; and
circuitry communicatively coupled to the management controller, the circuitry to:
dynamically generate a thermal model of multiple circuit blocks of a die based on layout information which identifies respective locations of the multiple circuit blocks, wherein the multiple circuit blocks comprise a first circuit block and one or more other circuit blocks which are proximate to the first circuit block, wherein the circuitry to generate the thermal model comprises the circuitry to:
calculate one or more thermal efficiency profiles each for a respective circuit block of the one or more other circuit blocks; and
calculate a first thermal efficiency profile for the first circuit block based on the one or more thermal efficiency profiles, wherein the first thermal efficiency profile identifies a thermal sensitivity of the first circuit block, and wherein the thermal sensitivity is based on the respective locations of the multiple circuit blocks; and
report a schedule recommendation to an operating system scheduler based at least in part on the thermal model.
2 . The integrated circuit of claim 1 , wherein the circuitry to dynamically generate the thermal model comprises the circuitry to:
dynamically estimate respective thermal sensitivities for each of the multiple circuit blocks based at least in part on the respective locations of the multiple circuit blocks.
3 . The integrated circuit of claim 1 , wherein the circuitry to dynamically generate the thermal model comprises the circuitry to:
calculate the first thermal efficiency profile based at least in part on an estimated recovery time of the first circuit block.
4 . The integrated circuit of claim 1 , wherein the circuitry to dynamically generate the thermal model comprises the circuitry to:
calculate the first thermal efficiency profile of the first circuit block based at least in part on activity on a second circuit block of the multiple circuit blocks.
5 . The integrated circuit of claim 1 , wherein the circuitry is further to:
determine the schedule recommendation further based at least in part on an application specific requirement.
6 . A method, comprising:
dynamically generating a thermal model of multiple circuit blocks of a die based on layout information which identifies respective locations of the multiple circuit blocks, wherein the multiple circuit blocks comprise a first circuit block and one or more other circuit blocks which are proximate to the first circuit block, wherein generating the thermal model comprises:
calculating one or more thermal efficiency profiles each for a respective circuit block of the one or more other circuit blocks; and
calculating a first thermal efficiency profile for the first circuit block based on the one or more thermal efficiency profiles, wherein the first thermal efficiency profile identifies a thermal sensitivity of the first circuit block, and wherein the thermal sensitivity is based on the respective locations of the multiple circuit blocks; and
reporting a schedule recommendation to an operating system scheduler based at least in part on the thermal model.
7 . The method of claim 6 , wherein dynamically generating the thermal model comprises:
dynamically estimating respective thermal sensitivities for each of the multiple circuit blocks based at least in part on the respective locations of the multiple circuit blocks.
8 . The method of claim 6 , wherein dynamically generating the thermal model comprises:
calculating the first thermal efficiency profile based at least in part on an estimated recovery time of the first circuit block.
9 . The method of claim 6 , wherein the schedule recommendation is reported to the operating system scheduler via a hardware-guided scheduler.
10 . An apparatus, comprising:
multiple circuit blocks arranged on a same substrate, the multiple circuit blocks comprising a first circuit block and one or more other circuit blocks which are proximate to the first circuit block; and
a management controller communicatively coupled to the multiple circuit blocks, the management controller including circuitry to:
dynamically generate a thermal model of the multiple circuit blocks based on layout information which identifies respective locations of the multiple circuit blocks, wherein the circuitry to generate the thermal model comprises the circuitry to:
calculate one or more thermal efficiency profiles each for a respective circuit block of the one or more other circuit blocks; and
calculate a first thermal efficiency profile for the first circuit block based on the one or more thermal efficiency profiles, wherein the first thermal efficiency profile identifies a thermal sensitivity of the first circuit block, and wherein the thermal sensitivity is based on the respective locations of the multiple circuit blocks; and
report a schedule recommendation to an operating system scheduler based at least in part on the thermal model.
11 . The apparatus of claim 10 , wherein the circuitry to dynamically generate the thermal model comprises the circuitry to:
dynamically estimate respective thermal sensitivities for each of the multiple circuit blocks based at least in part on the respective locations of the multiple circuit blocks.
12 . The apparatus of claim 10 , wherein the circuitry to dynamically generate the thermal model comprises the circuitry to:
calculate the first thermal efficiency profile based at least in part on an estimated recovery time of the first circuit block.
13 . The apparatus of claim 10 , wherein the circuitry to dynamically generate the thermal model comprises the circuitry to:
calculate the first thermal efficiency profile of the first circuit block based at least in part on activity on a second circuit block of the multiple circuit blocks.
14 . The apparatus of claim 13 , wherein the first circuit block comprises a core block and wherein the second circuit block comprises a non-core block.
15 . The apparatus of claim 10 , wherein the circuitry is to report the schedule recommendation to the operating system scheduler via a hardware-guided scheduler.