Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
Numerous examples of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a method for performing a read or verify operation in a vector-by-matrix multiplication system comprising an input function circuit, a memory array, and an output circuit block is disclosed, the method comprising receiving, by the input function circuit, digital bit input values; converting the digital input values into an input signal; applying the input signal to control gate terminals of selected cells in the memory array; and generating, by the output circuit block, an output value in response to currents received from the memory array.
1 . A method for performing a vector-by-matrix multiplication operation on a memory array using an input function circuit and an output circuit block, the method comprising:
receiving, by the input function circuit, a digital value to be applied as an input to a row in the memory array to perform a vector-by-matrix multiplication operation, the digital value comprising a sequence of bits, each of the bits having a respective bit position within the sequence of bits;
converting the sequence of bits into a sequence of analog input signals, each analog input signal in the sequence of analog input signals corresponding to a bit in the sequence of bits;
applying, sequentially, each analog input signal in the sequence of analog input signals to control gate terminals of the row; and
receiving, by the output circuit block, a sequence of output analog signals in response to the sequence of analog input signals and multiplying each output analog signal in the sequence of output analog signals by a respective factor corresponding to the respective bit position of the corresponding bit in the sequence of bits associated with the output analog signal and summing results of the multiplying to generate an output.
2 . The method of claim 1 , converting the output into a set of digital bits.
3 . The method of claim 1 , wherein the factor is one when the bit position is the first bit position within the sequence of bits.
4 . The method of claim 1 , wherein the factor is two when the bit position is the second bit position within the sequence of bits.
5 . The method of claim 1 , wherein the factor is 2 n when the bit position is the n-th bit position within the sequence of bits.
6 . The method of claim 1 , wherein each analog input signal comprises one or more pulses.
7 . The method of claim 6 , wherein the number of pulses generated are proportional to the value represented by the bit in the sequence of bits corresponding to the analog input signal.
8 . The method of claim 1 , wherein the output circuit block comprises an integrating analog-to-digital converter.
9 . The method of claim 1 , wherein the output circuit block comprises a successive approximation analog-to-digital converter.
10 . The method of claim 1 , wherein the output circuit block comprises a Sigma-Delta analog-to-digital converter.
11 . A method for performing vector-by-matrix multiplication operation on a memory array using an input function circuit and an output circuit block, the method comprising:
receiving, by the input function circuit, a digital value for a row in the array to perform a vector-by-matrix multiplication operation, the digital value comprising a sequence of bits, each of the bits having a respective bit position within the sequence of bits; and
for each bit in the sequence of bits:
converting the bit into an input signal;
applying the input signal to a terminal of selected cells in the row; and
modulating output currents on bit lines coupled to the selected cells with a respective pulsewidth proportional to the respective bit position of the bit within the sequence of bits to generate output voltages.
12 . The method of claim 11 , further comprising:
converting, by an analog-to-digital converter, each output voltage to a set of digital output bits.
13 . The method of claim 12 , further comprising:
summing the sets of digital output bits generated for the set of digital input bits to generate a digital output.
14 . The method of claim 11 , wherein each input signal is a voltage.
15 . The method of claim 11 , wherein each input signal comprises one or more digital pulses.
16 . The method of claim 12 , wherein the analog-to-digital converter comprises an integrating analog-to-digital converter.
17 . The method of claim 12 , wherein the analog-to-digital converter comprises a successive approximation analog-to-digital converter.
18 . The method of claim 12 , wherein the analog-to-digital converter comprises a Sigma-Delta analog-to-digital converter.