Defect detecting device and method
A test device includes a memory and a controller. The memory stores reference data including a reference image obtained by photographing a reference pattern on a first semiconductor sample, a first height of the reference pattern, a first shadow length of the reference pattern, and a reference value that represents a correlation between the first height and the first shadow length. The controller receives an image obtained by photographing a pattern on a second semiconductor sample, measures a second shadow length of the pattern from the image, and calculates a second height of the pattern from the second shadow length based on the reference data.
1 . A test device comprising:
a memory that stores reference data including a reference image obtained by photographing a reference pattern on a first semiconductor sample, a first height of the reference pattern, a first shadow length of the reference pattern, and a reference value that represents a correlation between the first height and the first shadow length that were previously measured from the reference pattern physically formed on the first semiconductor sample; and
a controller that is configured to receive an image obtained by photographing a pattern on a second semiconductor sample, measure a second shadow length of the pattern from the image, and calculate a second height of the pattern from the second shadow length by applying the reference value to the second shadow length.
2 . The test device of claim 1 , wherein:
the memory further stores a defect vulnerable region of a semiconductor device layout, the defect vulnerable region being a region in which a defect is more likely to occur than other regions of the semiconductor device layout, and
the controller is configured to determine the pattern to be a defect pattern when the second height is greater than a threshold value and the pattern on the second semiconductor sample is disposed in the defect vulnerable region.
3 . The test device of claim 2 , wherein the defect vulnerable region includes a region in which a first gate electrode crosses a second gate electrode.
4 . The test device of claim 2 , wherein the defect vulnerable region includes a region between a first gate electrode and a second gate electrode that is disposed near the first gate electrode and that is disposed in parallel to the first gate electrode.
5 . The test device of claim 2 , wherein the defect vulnerable region includes a region between a first via and a second via that is electrically connected to the first via.
6 . The test device of claim 1 , wherein the reference data further includes a first brightness value of the reference pattern, and the controller is configured to calculate the second height of the pattern on the second semiconductor sample based on the first brightness value.
7 . The test device of claim 1 , wherein the reference value is a tangent value obtained by dividing the first height by the first shadow length.
8 . The test device of claim 1 , wherein when the second height is greater than a threshold value, the pattern on the second semiconductor sample is a defect pattern.
9 . A defect detecting system comprising:
a lamp including a plurality of light sources and irradiating light onto a semiconductor sample;
a scanning electron microscope (SEM) device configured to generate an image, the image including a pattern formed on the semiconductor sample by the light and a second shadow of the pattern formed on the semiconductor sample by the light; and
a test device including a controller configured to receive the image, measure a second shadow length of the second shadow in the image, and calculate a second height of the pattern formed on the semiconductor sample by applying a reference value to the second shadow length, based on reference data that includes a first height of a reference pattern, a first shadow length of the reference pattern, and the reference value that represents a correlation between the first height and the first shadow length that were previously measured from the reference pattern physically formed on the semiconductor sample.
10 . The defect detecting system of claim 9 , wherein the reference value represents an angle between a surface of the semiconductor sample and a straight line that connects a first light source from among the plurality of light sources and the reference pattern.
11 . The defect detecting system of claim 9 , wherein the reference value is a tangent value obtained by dividing the first height by the first shadow length.
12 . The defect detecting system of claim 9 , wherein the test device is configured to determine that the pattern formed on the semiconductor sample is a defect pattern when the second height is greater than a threshold value.
13 . The defect detecting system of claim 9 , wherein the test device is configured to determine that the pattern formed on the semiconductor sample is a defect pattern when the second height is greater than a threshold value and the pattern formed on the semiconductor sample is disposed in a defect vulnerable region of a semiconductor device layout, the defect vulnerable region being a region in which a defect is more likely to occur than other regions of the semiconductor device layout.
14 . A method comprising:
generating an image of a semiconductor sample, the image including a pattern;
measuring a first shadow length of the pattern in the image;
calculating a height of the pattern by applying a reference value to the first shadow length based on reference data that includes a second height of a reference pattern corresponding to the first shadow length and the pattern included in the image, a second shadow length ofcaused by the reference pattern, and the reference value that represents a correlation between the second height and the second shadow length that were previously measured from the reference pattern physically formed on the semiconductor sample; and
determining that the pattern included in the image is a defect pattern when the height of the pattern included in the image is greater than a threshold value.
15 . The method of claim 14 , further comprising determining a defect vulnerable region in a layout image, the defect vulnerable region being a region in which a defect is more likely to occur than other regions of the layout image,
wherein the pattern included in the image is determined as the defect pattern when the pattern included in the image is included in the defect vulnerable region.
16 . The method of claim 15 , wherein determining the defect vulnerable region includes determining a region in which a first gate electrode crosses a second gate electrode to be the defect vulnerable region.
17 . The method of claim 15 , wherein determining the defect vulnerable region includes determining a region between a first gate electrode and a second gate electrode that is disposed near the first gate electrode and that is disposed in parallel to the first gate electrode to be the defect vulnerable region.
18 . The method of claim 15 , wherein determining the defect vulnerable region includes determining a region between a first via and a second via that is electrically connected to the first via to be the defect vulnerable region.
19 . The method of claim 14 , wherein the reference data further include a first brightness value on the reference pattern.
20 . The method of claim 14 , further comprising transmitting an equipment control signal for restoring the defect pattern into a normal pattern to processing equipment for performing a unit process on the semiconductor sample.