Integrated circuit device and operating method for decoding acceleration

1 . An integrated circuit device comprising:

a table storage subsystem for storing information associated with a code table, the table storage subsystem including:

code table storage for storing a plurality of symbol entries each containing a code symbol;

maximum code storage for storing a plurality of maximum values for different code lengths; and

offset storage for storing a plurality of offset values;

a plurality of comparators corresponding to the plurality of maximum values to concurrently compare input data to each of the maximum values to determine a code length value;

a plurality of index generation circuits corresponding to the plurality of offset values to concurrently generate a plurality of index values from the plurality of offset values and the input data; and

a selection circuit operable to use the determined code length value to select an index value from the plurality of index values,

wherein the index value is used to select a symbol entry from the code table storage for decoding a code in the input data.

2 . The integrated circuit device of claim 1 , wherein the plurality of symbol entries in the code table storage corresponds to codes greater than a threshold code length, and

wherein the table storage subsystem further includes lookahead table storage for storing a plurality of lookahead entries corresponding to codes less than or equal to the threshold code length.

3 . The integrated circuit device of claim 2 , wherein the threshold code length is n bits, and the lookahead table storage includes 2 n lookahead entries for each unique 8-bit sequence.

4 . The integrated circuit device of claim 2 , wherein each lookahead entry corresponding to a valid code includes a code symbol and a code length corresponding to a unique bit sequence of the threshold code length.

5 . The integrated circuit device of claim 4 , wherein each lookahead entry further includes a lookahead code hit indicator indicating whether the threshold code length of bits in the input data contains a valid code.

6 . The integrated circuit device of claim 5 , wherein the lookahead code hit indicator is used to select between the lookahead table storage and the code table storage as a source of a code symbol decoded from the input data.

7 . The integrated circuit device of claim 1 , wherein the table storage subsystem is one of a plurality of table storage subsystems for storing information associated with respective code tables.

8 . The integrated circuit device of claim 7 , wherein the integrated circuit device is operable to dynamically switch between the plurality of table storage subsystems being used to decode the input data.

9 . The integrated circuit device of claim 1 , wherein the input data includes a coefficient value that follows the code in the input data, and wherein a code symbol decoded from the code in the input data includes a first value representing a number of leading zeros before the coefficient value, and a second value representing a bit length of the coefficient value.

10 . The integrated circuit device of claim 9 , wherein the integrated circuit device is operable to write the coefficient value at a location in memory with an offset corresponding to the number of leading zeros.

11 . The integrated circuit device of claim 1 , wherein the integrated circuit device is operable to decode one code in the input data per clock cycle.

12 . A method for operating an integrated circuit device, the method comprising:

loading, by the integrated circuit device, code symbols associated with different code lengths into a code table of the integrated circuit device;

receiving, by the integrated circuit device, input data containing a code to decode; and

determining, by the integrated circuit device in one clock cycle, a code symbol corresponding to the code in the input data by:

concurrently comparing different bit lengths of the input data to maximum values for the different code lengths to determine a code length value;

concurrently generating a plurality of index values from a plurality of offset values and the input data;

selecting an index value from the plurality of index values using the determined code length value; and

selecting an entry in the code table using the index value.

13 . The method of claim 12 , wherein the code symbols loaded into the code table correspond to codes greater than a threshold code length,

wherein the method further includes loading, by the integrated circuit device, lookahead entries into a lookahead table, the lookahead entries corresponding to codes less than or equal to the threshold code length, and

wherein determining the code symbol includes determining whether a bit sequence of the input data of the threshold code length matches a valid code in the lookahead table.

14 . The method of claim 13 , wherein the code symbol corresponding to the code in the input data is selected from the lookahead table when the input data matches a valid code symbol in the lookahead table, and wherein the code symbol corresponding to the code in the input data is selected from the code table when the input data does not match a valid code in the lookahead table.

15 . The method of claim 12 , wherein the code table is one of a plurality of code tables, and

wherein the method further includes switching between the plurality of code tables used for decoding the input data based on a table sequence.

16 . The method of claim 12 , wherein the input data includes a coefficient value that follows the code in the input data,

wherein the code symbol includes a first value representing a number of leading zeros before the coefficient value, and a second value representing a bit length of the coefficient value, and

wherein the method further includes writing the coefficient value at a location in memory with an offset from a previous coefficient value, the offset corresponding to the number of leading zeros.

17 . The integrated circuit device of claim 1 , wherein a code length of the input data is determined from the comparison results of the comparators.

18 . The integrated circuit device of claim 1 , wherein the plurality of comparators has a same number of comparators as a number of index generation circuits in the plurality of index generation circuits.

19 . The integrated circuit device of claim 1 , wherein the plurality of index generation circuits is a set of adders operable to concurrently add different bit lengths of the input data respectively to the offset values corresponding to different code lengths.

20 . The integrated circuit device of claim 19 , further comprising padding logic to pad the different bit lengths of the input data.