Display panel, driving controller and pixel circuit driving method

1 . A pixel circuit driving method, comprising:

receiving an image signal by a control circuit, wherein the image signal comprises N pixel values;

using a first lookup table to obtain P voltage data corresponding to each of the N pixel values, wherein the P voltage data are respectively provided in P original frames during one update period, wherein each of the P original frames is divided into Q update frames, wherein N, P, and Q are integers greater than one;

using a second lookup table to generate, for each of the N pixel values, P voltage combinations corresponding to the respective P voltage data, wherein each of the P voltage combinations comprises Q update voltages provided respectively in the Q update frames;

generating the Q update voltages, by a plurality of power generating circuits, to a plurality of driving multiplexing circuits according to each of the P voltage combinations; and

using the Q update voltages in each of the P original frames as a respective driving voltage and providing the P driving voltages of the P original frames to a corresponding one of N pixel circuits by the plurality of power generating circuits.

2 . The pixel circuit driving method of claim 1 , wherein using the second lookup table to generate, for each of the N pixel values, the P voltage combinations corresponding to the respective P voltage data comprises:

using a subset of the voltage data corresponding to one of the P original frames for the N pixel values as the N update voltages in one of the Q update frames of said one of the P original frames, wherein each of the N update voltages corresponds to one of the N pixel values, wherein a number of the subset of the voltage data is equal to a number of the plurality of power generating circuits.

3 . The pixel circuit driving method of claim 2 , wherein one of the N update voltages is a reference voltage value of the N pixel circuits.

4 . The pixel circuit driving method of claim 3 , wherein each of the P voltage combinations comprises the reference voltage value.

5 . The pixel circuit driving method of claim 1 , wherein using the first lookup table to obtain the P voltage data corresponding to each of the N pixel values comprises:

obtaining a plurality of original encoding sequences corresponding to the N pixel values, wherein each of the plurality of original encoding sequences comprises a plurality of voltage codes, the plurality of voltage codes corresponds to the P original frames in sequence, and the original frames comprise a first original frame; and

using a subset of the plurality of voltage codes corresponding to the first original frame as the voltage data in the first original frame for the N pixel values.

6 . The pixel circuit driving method of claim 5 , wherein using the second lookup table to generate, for each of the N pixel values, the P voltage combinations corresponding to the respective P voltage data comprises:

using the second lookup table to generate the P voltage combinations according to the plurality of original encoding sequences.

7 . The pixel circuit driving method of claim 6 , further comprising:

converting each one of the plurality of original encoding sequences into a plurality of update encoding sequences formed by the P voltage combinations, wherein the Q update voltages of each of the P voltage combinations are generated by the plurality of power generating circuits based on the plurality of update encoding sequences.

8 . The pixel circuit driving method of claim 7 , wherein using the Q update voltages in each of the P original frames as the respective driving voltage and providing the P driving voltages of the P original frames to the corresponding one of the N pixel circuits comprises:

receiving, by the plurality of driving multiplexing circuits, all of the update voltages during one of the Q update frames, and selectively outputting one of all the update voltages to the corresponding one of the N pixel circuits.

9 . The pixel circuit driving method of claim 8 , wherein using the Q update voltages in each of the P original frames as the respective driving voltage and providing the P driving voltages of the P original frames to the corresponding one of the N pixel circuits comprises:

sequentially generating a plurality of timing selection signals during the Q update frames according to the plurality of update encoding sequences by a sequential circuit of the control circuit, so that the plurality of driving multiplexing circuits selectively output the one of all the update voltages.

10 . A driving controller, comprising:

a control circuit configured to receive an image signal, wherein the image signal comprises N pixel values;

a memory coupled to the control circuit, and recording a first lookup table and a second lookup table, wherein the control circuit is configured to use the first lookup table to obtain P voltage data corresponding to each of the N pixel values, wherein the P voltage data are respectively provided in P original frames during one update period, wherein each of the P original frames is divided into Q update frames, wherein N, P, and Q are integers greater than one;

wherein the control circuit is configured to use the second lookup table to generate, for each of the N pixel values, P voltage combinations corresponding to the respective P voltage data, wherein each of the P voltage combinations comprises Q update voltages provided respectively in the Q update frames;

a plurality of power generating circuits coupled to the control circuit, and configured to generate the Q update voltages according to each of the P voltage combinations; and

a plurality of driving multiplexing circuits coupled to the plurality of power generating circuits and N pixel circuits, and configured to use the Q update voltages generated by the plurality of power generating circuits in each of the P original frames as a respective driving voltage and provide the P driving voltages of the P original frames to a corresponding one of the N pixel circuits.

11 . A display panel, comprising:

N pixel circuits; and

a driving controller coupled to the N pixel circuits, and configured to receive an image signal, wherein the image signal comprises N pixel values, and each of the N pixel values corresponds to P voltage data, wherein the N pixel circuits respectively display the N pixel values during an update period, wherein the update period comprises P original frames and each of the P original frames is divided into Q update frames, wherein each of the N pixel values corresponds to a combination of P voltage data in the P original frames, respectively, wherein N, P, and Q are integers greater than one;

wherein the driving controller is configured to convert the P voltage data into P voltage combinations, and is configured to generate Q update voltages respectively in the Q update frames of each of the P original frames for each of the N pixel circuits, wherein a combination of the Q update voltages corresponds to one of the P voltage combinations.

12 . The display panel of claim 11 , wherein the driving controller is configured to obtain a plurality of original encoding sequences corresponding to the N pixel values, and each of the plurality of original encoding sequences is formed by the P voltage data in the P original frames corresponding to one of the N pixel values; and

wherein the driving controller is further configured to convert each of the plurality of original encoding sequences into a plurality of update encoding sequences.

13 . A display panel, comprising:

N pixel circuits; and

a driving controller coupled to the N pixel circuits, and configured to receive an image signal, wherein the image signal comprises N pixel values, wherein the N pixel circuits respectively display the N pixel values during an update period;

wherein the update period comprises P original frames and each of the P original frames is divided into Q update frames, wherein each of the N pixel values corresponds to a combination of P driving voltages in the P original frames, respectively, wherein N, P, and Q are integers greater than one;

wherein the driving controller is configured to generate Q update voltages respectively in the Q update frames of each of the P original frames for each of the N pixel circuits, wherein a combination of the Q update voltages corresponds to one of the P driving voltages;

wherein for the N pixel circuits, in a same one of the Q update frames of one of the P original frames, the update voltages provided by the driving controller comprise a reference voltage value and a plurality of symmetrical voltage groups, and each group of the plurality of symmetrical voltage groups comprises two voltages that have a same value but are positive and negative to each other.