Display panel, method for driving display panel, and display apparatus

1 . A display panel comprising:

a driver circuit, the driver circuit comprising a plurality of stages of shift register units which each comprise an input module, an output module, a signal input terminal, a first clock terminal, a first level terminal, and a signal output terminal;

in each of the shift register units, the input module being electrically connected to the signal input terminal and the output module, and the input module and the output module being electrically connected to a first node; the output module being electrically connected to the first node, the first clock terminal, and the signal output terminal; the first clock terminal being configured to receive a first clock signal; and the first level terminal being configured to receive a first level signal;

at least a part of the shift register units being first-type shift register units which each further comprise a restoration module and a restoration signal terminal; in each of the first-type shift register units, the restoration module being electrically connected to the restoration signal terminal and the first level terminal, and the restoration module being further electrically connected to the first node and/or the signal output terminal; and the restoration signal terminal being configured to receive a restoration signal;

the signal output terminal of the i-th stage of the shift register units being electrically connected to the signal input terminal of the (i+N)-th stage of the shift register units, where i and N are both positive integers;

a plurality of stages of the first-type shift register units comprising at least one stage of first shift register unit and at least one stage of second shift register unit;

the restoration signal of the second shift register unit comprising a first active pulse, and at least within a time period in which the first active pulse of the restoration signal of the second shift register unit is, the restoration signal of the first shift register unit being at an inactive level; and a starting moment of the first active pulse being before a starting moment of a starting active pulse of the first clock signal of the at least one stage of first shift register unit; and

wherein a first level signal line and a restoration signal line which are insulated from each other; the first level terminal of the at least one stage of first shift register unit and the first level terminal of the at least one stage of second shift register unit being both electrically connected to the first level signal line; the restoration signal terminal of the at least one stage of first shift register unit being electrically connected to the first level signal line; and the restoration signal terminal of the at least one stage of second shift register unit being electrically connected to the restoration signal line.

2 . The display panel according to claim 1 , wherein the first active pulse overlaps the starting active pulse of the first clock signal of the at least one stage of first shift register unit.

3 . The display panel according to claim 1 , wherein the first stage of the first-type shift register units to the L-th stage of the first-type shift register units are the first shift register units, and L is a positive integer; and the starting moment of the first active pulse is before a starting moment of the starting active pulse of the first clock signal which is received by the first stage of the first-type shift register units.

4 . The display panel according to claim 1 , further comprising: a start signal line for transmitting a start control signal; and the signal input terminals of the first stage of the shift register units to the N-th stage of the shift register units being all electrically connected to the start signal line.

5 . The display panel according to claim 4 , wherein a starting moment of an active pulse of the start control signal is before a starting moment of a starting active pulse of the first clock signal which is received by the first stage of the shift register units, and a terminating moment of the active pulse of the start control signal is before a terminating moment of the starting active pulse of the first clock signal which is received by the first stage of the shift register units.

6 . The display panel according to claim 4 , wherein a time length of a clock cycle of the first clock signal is 2*N*H, and a time length of an active pulse of the first clock signal is N*H, where H is one clock unit time length; and a time interval between the starting moment of the active pulse of the start control signal and the starting moment of the starting active pulse of the first clock signal which is received by the first stage of the shift register units is greater than or equal to N*H.

7 . The display panel according to claim 4 , wherein the starting moment of the first active pulse and the starting moment of the active pulse of the start control signal are the same moment.

8 . The display panel according to claim 1 , wherein a duration of the first active pulse overlaps durations of the active pulses of the first clock signals of the first stage of the shift register units to the M-th stage of the shift register units, and the duration of the first active pulse does not overlap a duration of an active pulse of the first clock signal of the (M+1)-th stage of the shift register units, where M≤N, and M is a positive integer; and the first stage of the shift register units to the (M+N)-th stage of the shift register units are all the first shift register units.

9 . The display panel according to claim 1 , wherein a duration of the first active pulse overlaps durations of the active pulses of the first clock signals of the first stage of the shift register units to the P-th stage of the shift register units, and the duration of the first active pulse does not overlap a duration of an active pulse of the first clock signal of the (P+1)-th stage of the shift register units, where N<P≤2N, ≤ and P is a positive integer; and the first stage of the shift register units to the (P+N)-th stage of the shift register units are all the first shift register units.

10 . The display panel according to claim 1 , wherein the shift register units each further comprise a pull-down module and a pull-down control module; in a same one of the shift register units, the pull-down control module is electrically connected to at least the first node, a second node, and the first level terminal; and the pull-down module is electrically connected to the first level terminal, the second node, the first node, and the signal output terminal; the pull-down control module comprises a first transistor, a second transistor, a third transistor, and a fourth transistor; a first electrode of the first transistor is connected to a first signal terminal, a second electrode of the first transistor is connected to a gate of the second transistor, and a gate of the first transistor is connected to a second signal terminal; a first electrode of the second transistor is connected to a third signal terminal, and a second electrode of the second transistor is connected to the second node; gates of the third transistor and the fourth transistor are both electrically connected to the first node; a first electrode of the third transistor and a first electrode of the fourth transistor are both electrically connected to the first level terminal; a second electrode of the third transistor is electrically connected to the second node, and a second electrode of the fourth transistor is electrically connected to the gate of the second transistor; the shift register units each further comprise a second clock terminal which is electrically connected to the second clock terminal and is configured to receive a second clock signal; and the first signal terminal and the third signal terminal are both electrically connected to the second clock terminal; or the shift register units each further comprise a second level terminal which is configured to receive a second level signal, and the first signal terminal and the third signal terminal are both electrically connected to the second level terminal; or the shift register units each further comprise a second level terminal which is configured to receive a second level signal, and the first signal terminal, the second signal terminal, and the third signal terminal are all electrically connected to the second level terminal.

11 . The display panel according to claim 1 , wherein the restoration module comprises: a sixth transistor, a first electrode of the sixth transistor being electrically connected to the first level terminal, a second electrode of the sixth transistor being electrically connected to the first node, and a gate of the sixth transistor being electrically connected to the restoration signal terminal; and/or, a seventh transistor, a first electrode of the seventh transistor being electrically connected to the first level terminal, a second electrode of the seventh transistor being electrically connected to the signal output terminal, and a gate of the seventh transistor being electrically connected to the restoration signal terminal.

12 . The display panel according to claim 1 , wherein the shift register units each further comprise a first reset module and a first reset signal terminal; in a same one of the shift register units, the first reset module is electrically connected to the first reset signal terminal, the first level terminal, and the first node; the first reset signal terminal is configured to receive a first reset signal; at least part of a duration of an active pulse of a gate driving signal which is output by the signal output terminal does not overlap a duration of an active pulse of the first reset signal; the first reset signal terminal of the i-th stage of the shift register units is electrically connected to the signal output terminal of the j-th stage of the shift register units, where j>i, and i and j are both positive integers; and j=i+orj=i+1.

13 . The display panel according to claim 1 , wherein the shift register units each further comprise a third reset module and a third reset signal terminal, the third reset module is electrically connected to the third reset signal terminal, the third level terminal, and a second side signal output terminal, and the signal output terminal of each of the shift register units is a first side signal output terminal; the display panel further comprises a plurality of gate signal lines and a plurality of pixels, the gate signal lines are electrically connected to the pixels, and the gate signal lines are electrically connected to the first side signal output terminals and the second side signal output terminals; and along an extension direction of the gate signal lines, the output modules and the third reset modules of the shift register units are located on two opposite sides of the gate signal lines, respectively.

14 . The display panel according to claim 1 , wherein the display panel further comprises a plurality of gate signal lines, a plurality of pixels, and a first reset signal line, and the gate signal lines are electrically connected to the pixels; the second shift register units comprise a driving shift register unit and a dummy shift register unit, the driving shift register unit provides a gate driving signal to the gate signal lines, and the dummy shift register unit does not provide a gate driving signal to the gate signal lines; the driving shift register unit and the dummy shift register unit each further comprise a first reset module and a first reset signal terminal; in a same one of the shift register units, the first reset module is electrically connected to the first reset signal terminal, the first level terminal, and the first node; the i-th stage of the shift register units is the driving shift register unit, and the first reset signal terminal of the i-th stage of the shift register units is electrically connected to the signal output terminal of the j-th stage of the shift register units, where i and j are both positive integers, and i+N≤j<i+2N; the p-th stage of the shift register units is the dummy shift register unit, and the first reset signal terminal of the p-th stage of the shift register units is electrically connected to the first reset signal line, where p is a positive integer; and the first reset signal line provides a reset active pulse which is the same as the first active pulse.

15 . The display panel according to claim 1 , wherein the restoration signal which is received by the second shift register units further comprises a second active pulse; an operation process of the display panel comprises a frame period which comprises the first active pulse and the second active pulse; and a starting moment of the second active pulse is after a terminating moment of an active pulse of a gate driving signal which is output by each of the stages of shift register units.

16 . A display panel, comprising:

a driver circuit, a first restoration signal line, and a second restoration signal line;

the driver circuit comprising a plurality of stages of shift register units which each comprise an input module, an output module, a signal input terminal, a first clock terminal, a first level terminal, and a signal output terminal;

in each of the shift register units, the input module being electrically connected to the signal input terminal and the output module, and the input module and the output module being electrically connected to a first node; the output module being electrically connected to the first node, the first clock terminal, and the signal output terminal; the first level terminal being configured to receive a first level signal; and the first clock terminal being configured to receive a first clock signal;

at least a part of the shift register units being first-type shift register units which each further comprise a restoration module and a restoration signal terminal; in each of the first-type shift register units, the restoration module being electrically connected to the restoration signal terminal and the first level terminal, and the restoration module being further electrically connected to the first node and/or the signal output terminal; and the restoration signal terminal being configured to receive a restoration signal;

a plurality of stages of the first-type shift register units comprising at least one stage of first shift register unit and at least one stage of second shift register unit;

the restoration signal terminal of the first shift register unit being electrically connected to the first restoration signal line; and the restoration signal terminal of the second shift register unit being electrically connected to the second restoration signal line;

the first restoration signal line and the second restoration signal line are insulated from each other; and

a first level signal line, the first level terminal of the at least one stage of first shift register unit and the first level terminal of the at least one stage of second shift register unit being both electrically connected to the first level signal line; and the first restoration signal line being electrically connected to the first level signal line.

17 . A display apparatus, comprising a display panel, the display panel comprising:

a driver circuit, the driver circuit comprising a plurality of stages of shift register units which each comprise an input module, an output module, a signal input terminal, a first clock terminal, a first level terminal, and a signal output terminal;

in each of the shift register units, the input module being electrically connected to the signal input terminal and the output module, and the input module and the output module being electrically connected to a first node; the output module being electrically connected to the first node, the first clock terminal, and the signal output terminal; the first clock terminal being configured to receive a first clock signal; and the first level terminal being configured to receive a first level signal;

at least a part of the shift register units being first-type shift register units which each further comprise a restoration module and a restoration signal terminal; in each of the first-type shift register units, the restoration module being electrically connected to the restoration signal terminal and the first level terminal, and the restoration module being further electrically connected to the first node and/or the signal output terminal; and the restoration signal terminal being configured to receive a restoration signal;

the signal output terminal of the i-th stage of the shift register units being electrically connected to the signal input terminal of the (i+N)-th stage of the shift register units; and i and N being both positive integers;

a plurality of stages of the first-type shift register units comprising at least one stage of first shift register unit and at least one stage of second shift register unit; and

the restoration signal of the second shift register unit comprising at least a first active pulse, and at least within a time period in which the first active pulse of the restoration signal of the second shift register unit is, the restoration signal of the first shift register unit being at an inactive level;

a starting moment of the first active pulse being before a starting moment of a starting active pulse of the first clock signal of the at least one stage of first shift register unit; and

a first level signal line, the first level terminal of the at least one stage of first shift register unit and the first level terminal of the at least one stage of second shift register unit being both electrically connected to the first level signal line; and the first restoration signal line being electrically connected to the first level signal line.