Display driving apparatus and method capable of controlling pixel brightness
A display driving apparatus according to an embodiment of the disclosure includes: a pixel driving circuit connected to each of a plurality of light-emitting diodes (LEDs) forming at least one row and column and configured to drive the LEDs in a pulse width modulation (PWM) method; a controller configured to determine a PWM duty ratio (PWM On-duty) indicating a light emitting time period of the LED during one frame section; and a timing controller configured to generate a first clock signal according to the PWM duty ratio and supply the first clock signal to the pixel driving circuit in a row or column unit through a shift register, wherein, when the PWM duty ratio is changed, the timing controller is configured to generate a second clock signal matching the changed PWM duty ratio, and selectively supply the first clock signal or the second clock signal to the pixel driving circuit.
1 . A display driving apparatus comprising:
a pixel driving circuit connected to each of a plurality of light-emitting diodes (LEDs) forming at least one row and column and configured to drive the LEDs in a pulse width modulation (PWM) method;
a controller configured to determine a PWM duty ratio (PWM On-duty) indicating a light emitting time period of the LED during one frame section; and
a timing controller configured to generate a first clock signal according to the PWM duty ratio and supply the first clock signal to the pixel driving circuit in a row or column unit through a shift register,
wherein, when the PWM duty ratio is changed, the timing controller is configured to generate a second clock signal matching the changed PWM duty ratio, and selectively supply the first clock signal or the second clock signal to the pixel driving circuit.
2 . The display driving apparatus of claim 1 , wherein
the timing controller comprises:
at least one flipflop including an output terminal connected to the pixel driving circuit; and
at least one multiplexer (MUX) for selecting a clock signal input to a clock terminal of the at least one flipflop.
3 . The display driving apparatus of claim 2 , wherein
the timing controller comprises:
a pulse signal input terminal to which a pulse signal corresponding to the brightness of the LED is input; and
at least one clock input terminal to which a plurality of clock signals are input.
4 . The display driving apparatus of claim 3 , wherein
the MUX is configured to receive the plurality of clock signals from the at least one clock input terminal, and select one clock signal input to the clock terminal of the at least one flipflop, from among the plurality of clock signals.
5 . The display driving apparatus of claim 4 , wherein
the MUX is configured to select one clock signal input to the clock terminal of the at least one flipflop by using a switch.
6 . The display driving apparatus of claim 1 , wherein
the timing controller is configured to
generate a first clock signal according to the PWM duty ratio, generate a PWM clock signal based on the first clock signal through the shift register, and supply the PWM clock signal to the pixel driving circuit in a row or column unit, and
when the PWM duty ratio is changed, generate a second clock signal matching the changed PWM duty ratio, select the first clock signal or the second clock signal, generate a PWM clock signal based on the selected clock signal, and supply the PWM clock signal to the pixel driving circuit.
7 . The display driving apparatus of claim 1 , wherein
the timing controller is configured to generate a first selection signal for selecting the first clock signal and a second selection signal for selecting the second clock signal, and selectively supply the first clock signal and the second clock signal to the pixel driving circuit based on the first selection signal and the second selection signal, and
the first clock signal and the second clock signal are operated independently from each other with respect to the pixel driving circuit.
8 . The display driving apparatus of claim 1 , wherein
the timing controller comprises:
a clock signal selector configured to output a selection signal for selecting a first clock signal or a second clock signal based on driving information of the pixel driving circuit; and
a MUX configured to output the first clock signal or the second clock signal based on the selection signal output from the clock signal selection unit.
9 . A display driving apparatus comprising:
a pixel driving circuit connected to each of a plurality of light-emitting diodes (LEDs) forming at least one row and column and configured to drive the LEDs in a pulse width modulation (PWM) method;
a scan driving circuit configured to sequentially output a first signal to LEDs arranged in a first direction, from among the LEDs connected to the pixel driving circuit;
a data driving circuit configured to output a second signal to LEDs arranged in a second direction, from among the LEDs connected to the pixel driving circuit; and
the timing controller according to claim 1 .
10 . A method of controlling a display driving apparatus, the method comprising:
receiving a first clock signal corresponding to a first frame section and a second clock signal corresponding to a second frame section that is consecutive to the first frame section;
receiving a first selection signal;
a first frame driving step, in which the first selection signal is transferred to a selection signal shift register that corresponds to a first row of a plurality of light-emitting diodes (LEDs), a first clock signal is selected based on the first selection signal, and the first clock signal is transferred to a clock signal shift register connected to the first row;
sequentially performing the first frame driving step up to an N-th row of the plurality of LEDs during the first frame section;
receiving a second selection signal;
a second frame driving step, in which the second selection signal is transferred to a selection signal shift register corresponding to the first row, the second clock signal is selected based on the second selection signal, and the second clock signal is transferred to the clock signal shift register connected to the first row; and
sequentially performing the second frame driving step up to the N-th row during a second frame section,
wherein at least one row in which the first frame driving step and the second frame driving step overlap each other is driven only by the first clock signal.