Display panel, driving method thereof, and display device

1 . A display panel, comprising a pixel circuit and a light-emitting element; wherein

the pixel circuit comprises an amplitude modulation subcircuit and a pulse width modulation subcircuit;

the amplitude modulation subcircuit is connected to a first data signal line, and the pulse width modulation subcircuit is connected to a second data signal line; and

the amplitude modulation subcircuit comprises a first drive module and a first data writing module, and the first drive module comprises a first drive transistor;

the pulse width modulation subcircuit comprises a second drive module and a second data writing module, and the second drive module comprises a second drive transistor;

at least one of the following is satisfied;

an operating process of the pixel circuit comprises a first data writing stage and a first bias stage; in the first data writing stage, the first data writing module provides a first data signal to the first drive transistor; and in the first bias stage, the first data writing module provides a first bias adjustment signal to the first drive transistor;

or,

an operating process of the pixel circuit comprises a second data writing stage and a second bias stage; in the second data writing stage, the second data writing module provides a second data signal to the second drive transistor; and in the second bias stage, the second data writing module provides a second bias adjustment signal to the second drive transistor;

or,

the first data writing module comprises a first data writing transistor and a first bias transistor, the first data writing transistor provides a first data signal to a first drive transistor, and the first bias transistor provides a first bias adjustment signal to the first drive transistor;

or,

the second data writing module comprises a second data writing transistor and a second bias transistor, the second data writing transistor provides a second data signal to a second drive transistor, and the second bias transistor provides a second bias adjustment signal to the second drive transistor.

2 . The display panel of claim 1 , wherein

the first data writing module is connected to the first data signal line and provides the first data signal to the first drive transistor;

and

the second data writing module is connected to the second data signal line and is configured to provide the second data signal and the second bias adjustment signal to the second drive transistor.

3 . The display panel of claim 2 , wherein

at least two of the first data signal, the second data signal, and the second bias adjustment signal are provided by a same data signal line.

4 . The display panel of claim 3 , wherein

the first data signal and the second bias adjustment signal are provided by the first data signal line.

5 . The display panel of claim 2 , wherein

the first data writing module further provides the first bias adjustment signal to the first drive transistor; and

the first data signal line is configured to provide the first data signal, the first bias adjustment signal, and the second bias adjustment signal.

6 . The display panel of claim 5 , wherein

the first bias transistor and the second bias transistor are connected to a same scanning line.

7 . The display panel of claim 6 , wherein

within a period of one frame, an operating process of the display panel comprises a first period;

the display panel comprises a plurality of rows of pixel circuits; and

in the first period, first bias transistors in the plurality of rows of pixel circuits and second bias transistors in the plurality of rows of pixel circuits are turned on simultaneously.

8 . The display panel of claim 7 , wherein

within the period of one frame, the operating process of the display panel further comprises a second period and a third period;

in the second period, second data writing transistors in the plurality of rows of pixel circuits are turned on row by row, and in the third period, the light-emitting element emits light; and

at least one first period is located between the second period and the third period.

9 . The display panel of claim 2 , wherein

the first data signal line is configured to transmit the first data signal and the first bias adjustment signal in a time-sharing manner, and the second data signal line is configured to transmit the second data signal and the second bias adjustment signal in a time-sharing manner.

10 . The display panel of claim 9 , wherein

the display panel comprises a plurality of rows of pixel circuits; and

within a period of one frame, first data writing modules in the plurality of rows of pixel circuits are turned on simultaneously, and second data writing modules in the plurality of rows of pixel circuits are turned on row by row.

11 . The display panel of claim 9 , wherein

the first bias transistor and the second bias transistor are connected to different scanning lines.

12 . The display panel of claim 11 , wherein

within a period of one frame, an operating process of the display panel comprises a fourth period and a fifth period, and the fourth period and the fifth period do not overlap;

the display panel comprises a plurality of rows of pixel circuits;

in the fourth period, first bias transistors in the plurality of rows of pixel circuits are turned on simultaneously; and

in the fifth period, second bias transistors in the plurality of rows of pixel circuits are turned on row by row.

13 . The display panel of claim 2 , wherein

the first data writing module further provides the first bias adjustment signal to the first drive transistor; and

the second data signal line is configured to transmit the second data signal and the first bias adjustment signal.

14 . The display panel of claim 13 , wherein the display panel comprises a plurality of rows of pixel circuits; and

within a period of one frame, first data writing signals in the plurality of rows of pixel circuits are written row by row, and second data writing signals in the plurality of rows of pixel circuits are written simultaneously.

15 . The display panel of claim 1 , wherein

the data signal comprises a first data signal and a second data signal, the first data signal is provided to the amplitude modulation subcircuit, and the second data signal is provided to the pulse width modulation subcircuit; and

the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is provided to the amplitude modulation subcircuit, and the second bias adjustment signal is provided to the pulse width modulation subcircuit.

16 . The display panel of claim 1 , wherein

at least one of the first data signal line or the second data signal line is configured to transmit a data signal and a bias adjustment signal;

the data signal and the bias adjustment signal are at least transmitted simultaneously; or,

the data signal and the bias adjustment signal are transmitted in a time-sharing manner.

17 . A display device, comprising the display panel of claim 1 .

18 . A display panel, comprising a pixel circuit and a light-emitting element; wherein

the pixel circuit comprises an amplitude modulation subcircuit and a pulse width modulation subcircuit;

the amplitude modulation subcircuit is connected to a first data signal line, and the pulse width modulation subcircuit is connected to a second data signal line;

the amplitude modulation subcircuit comprises a first drive module and a first data writing module, and the first drive module comprises a first drive transistor;

the first data writing module is connected to the first data signal line and provides a first data signal to the first drive transistor;

the pulse width modulation subcircuit comprises a second drive module and a second data writing module, and the second drive module comprises a second drive transistor;

the second data writing module is connected to the second data signal line and is configured to provide a second data signal and a second bias adjustment signal to the second drive transistor; and

the first data signal and the second bias adjustment signal are provided by the first data signal line.

19 . The display panel of claim 18 , wherein the first data writing module further provides a first bias adjustment signal to the first drive transistor; and

the first data signal line is configured to provide the first data signal, the first bias adjustment signal, and the second bias adjustment signal.

20 . A display panel, comprising a pixel circuit and a light-emitting element; wherein

the pixel circuit comprises an amplitude modulation subcircuit and a pulse width modulation subcircuit;

the amplitude modulation subcircuit is connected to a first data signal line, and the pulse width modulation subcircuit is connected to a second data signal line;

the amplitude modulation subcircuit comprises a first drive module and a first data writing module, and the first drive module comprises a first drive transistor;

the first data writing module is connected to the first data signal line and is configured to provide a first data signal to the first drive transistor;

the pulse width modulation subcircuit comprises a second drive module and a second data writing module, and the second drive module comprises a second drive transistor;

the second data writing module is connected to the second data signal line and is configured to provide a second data signal to the second drive transistor;

wherein the display panel comprises a plurality of rows of pixel circuits; and

within a period of one frame, first data writing signals in the plurality of rows of pixel circuits are written row by row, and second data writing signals in the plurality of rows of pixel circuits are written simultaneously.