Pixel circuit having a capacitor structure and display device including the same
A pixel circuit and a display device are disclosed. A display device may include a plurality of subpixels that each include: a light emitting element; a driving transistor configured to operate the light-emitting element by receiving a data voltage; a switching transistor configured to apply the data voltage to a gate electrode of the driving transistor; the light-emitting element including a cathode and an anode, the anode being connected to a source electrode of the driving transistor, the cathode being electrically connected to a low-potential voltage supply line, in which the low-potential voltage supply line supplies a low-potential voltage to the light-emitting element, and in which an intermediate electrode line that traverses a storage capacitor of the subpixels composes a first parasitic capacitor with the gate electrode of the driving transistor and composes a second parasitic capacitor with the source electrode of the driving transistor.
1 . A display device comprising:
a plurality of subpixels; and
an intermediate electrode line traversing storage capacitors in storage capacitor areas of the plurality of subpixels,
wherein each of the plurality of subpixels includes:
a light-emitting element including a cathode and an anode;
a driving transistor configured to operate the light-emitting element by receiving a data voltage;
a switching transistor configured to apply the data voltage to a gate electrode of the driving transistor;
a storage capacitor having a first end connected to the gate electrode of the driving transistor and a second end connected to a source electrode of the driving transistor;
a first parasitic capacitor having a first end connected to the gate electrode of the driving transistor and to the first end of the storage capacitor; and
a second parasitic capacitor having a first end connected to the source electrode of the driving transistor and to the second end of the storage capacitor,
wherein the anode is connected to the source electrode of the driving transistor,
wherein the cathode is connected to a low-potential voltage supply line,
wherein the low-potential voltage supply line supplies a low-potential voltage to the light-emitting element,
wherein a second end of the first parasitic capacitor is connected to a second end of the second parasitic capacitor,
wherein the storage capacitor includes a first layer and a second layer forming a capacitor,
wherein the intermediate electrode line passes between the first layer and the second layer of the storage capacitor, and
wherein the intermediate electrode line composes the first parasitic capacitor with the gate electrode of the driving transistor and composes the second parasitic capacitor with the source electrode of the driving transistor.
2 . The display device of claim 1 , wherein the low-potential voltage supply line is electrically connected to the intermediate electrode line.
3 . The display device of claim 1 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to a high-potential voltage supply line.
4 . The display device of claim 1 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to a gate line configured to supply a scan signal or a sensing signal.
5 . The display device of claim 1 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to an initialization line configured to supply an initialization voltage.
6 . The display device of claim 1 , further comprising:
a high-potential voltage supply line,
wherein the gate electrode of the driving transistor is connected to a source electrode of a switching transistor, a drain electrode of the driving transistor is connected to the high-potential voltage supply line, and the source electrode of the driving transistor is connected to the anode of the light-emitting element.
7 . The display device of claim 6 , wherein the intermediate electrode line is disposed from the low-potential voltage supply line without intersecting the high-potential voltage supply line.
8 . The display device of claim 1 , further comprising:
a gate line configured to supply a scan signal or a sensing signal; and
a data line configured to supply the data voltage,
wherein a gate electrode of the switching transistor is connected to the gate line, a drain electrode of the switching transistor is connected to the data line, and a source electrode of the switching transistor is connected to the gate electrode of the driving transistor.
9 . The display device of claim 8 , wherein the intermediate electrode line is in parallel with the gate line.
10 . The display device of claim 8 , wherein a group of the plurality of subpixels composes one pixel, and the intermediate electrode line intersects a plurality of data lines included in the one pixel.
11 . The display device of claim 10 , wherein the plurality of subpixels comprise a first subpixel, a second subpixel, and a third subpixel,
wherein the plurality of data lines comprise a first data line for the first subpixel, a second data line for the second subpixel, and a third data line for the third subpixel, and
wherein a reference voltage line is between the first subpixel and the second subpixel and supplies a reference voltage to the first subpixel to the third subpixel.
12 . The display device of claim 11 , wherein the intermediate electrode line intersects the reference voltage line.
13 . The display device of claim 11 , wherein the third subpixel is spaced apart from the reference voltage line by a dimension of one subpixel.
14 . The display device of claim 8 , further comprising:
a sensing transistor configured to control a voltage state of the source electrode of the driving transistor,
wherein the sensing transistor is connected to the source electrode of the driving transistor and a reference voltage line that is configured to supply a reference voltage, and a gate electrode of the sensing transistor is connected to the gate line.
15 . The display device of claim 1 , further comprising:
a first wiring layer, an active layer, a second wiring layer, an intermediate electrode layer, and a third wiring layer sequentially disposed on a substrate,
wherein the storage capacitor in a storage capacitor area is made by coupling a first-first capacitor that is between the third wiring layer and the active layer, and a first-second capacitor that is between the first wiring layer and the active layer.
16 . The display device of claim 15 , wherein the first wiring layer is formed together with a high-potential voltage supply line, the low-potential voltage supply line, a data line, and a reference voltage line.
17 . The display device of claim 15 , wherein the active layer is a semiconductor layer for a plurality of transistors including a driving transistor.
18 . The display device of claim 15 , wherein the second wiring layer is formed together with a gate line.
19 . The display device of claim 15 , wherein the third wiring layer electrically connects the first wiring layer, the second wiring layer, the intermediate electrode layer, and the active layer through a plurality of contact holes.
20 . The display device of claim 15 , wherein the first parasitic capacitor is formed between the active layer and the intermediate electrode layer in the storage capacitor area.
21 . The display device of claim 15 , wherein the second parasitic capacitor is formed between the intermediate electrode layer and the third wiring layer in the storage capacitor area.
22 . The display device of claim 15 , wherein the intermediate electrode layer is between a first intermediate insulation layer and a second intermediate insulation layer.
23 . The display device of claim 22 , wherein the second wiring layer is between a gate insulation layer and the first intermediate insulation layer, and the third wiring layer is on the second intermediate insulation layer and covered by a passivation layer.
24 . A pixel circuit comprising:
a light-emitting element including a cathode and an anode;
a driving transistor configured to operate the light-emitting element by receiving a data voltage;
a switching transistor configured to apply the data voltage to a gate electrode of the driving transistor;
a storage capacitor having a first end connected to the gate electrode of the driving transistor and a second end connected to a source electrode of the driving transistor;
an intermediate electrode line traversing the storage capacitor in a storage capacitor area;
a first parasitic capacitor having a first end connected to the gate electrode of the driving transistor and to the first end of the storage capacitor; and
a second parasitic capacitor having a first end connected to the source electrode of the driving transistor and to the second end of the storage capacitor,
wherein the light-emitting element comprises a cathode and an anode,
wherein the anode is connected to a source electrode of the driving transistor,
wherein the cathode is connected to a low-potential voltage supply line that supplies a low-potential voltage to the light-emitting element,
wherein a second end of the first parasitic capacitor is connected to a second end of the second parasitic capacitor,
wherein the storage capacitor includes a first layer and a second layer forming a capacitor,
wherein the intermediate electrode line passes between the first layer and the second layer of the storage capacitor, and
wherein the intermediate electrode line composes the first parasitic capacitor with the gate electrode of the driving transistor and composes the second parasitic capacitor with the source electrode of the driving transistor.
25 . The pixel circuit of claim 24 , wherein the low-potential voltage supply line is electrically connected to the intermediate electrode line.
26 . The pixel circuit of claim 24 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to a high-potential voltage supply line.
27 . The pixel circuit of claim 24 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically to a gate line that is configured to supply a scan signal or a sensing signal.
28 . The pixel circuit of claim 24 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to an initialization line that is configured to supply an initialization voltage.
29 . The pixel circuit of claim 24 , further comprising:
a high-potential voltage supply line,
wherein the gate electrode of the driving transistor is connected to a source electrode of a switching transistor, a drain electrode of the driving transistor is connected to the high-potential voltage supply line, and the source electrode of the driving transistor is connected to the anode of the light-emitting element.
30 . The pixel circuit of claim 24 , wherein the storage capacitor comprises a first-first capacitor between the gate electrode and the source electrode of the driving transistor, and a first-second capacitor between the source electrode of the driving transistor and the low-potential voltage supply line.