Gate signal masking circuit, gate emission driver including the same and display apparatus including the same

1 . A gate signal masking circuit comprising:

a first switching element including a control electrode connected to a masking control node, a first electrode connected to a first input node and a second electrode connected to an output control node;

a second switching element including a control electrode connected to a second input node, a first electrode which receives a first power voltage and a second electrode connected to a first intermediate node;

a third switching element including a control electrode which receives an enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the masking control node;

a fourth switching element including a control electrode which receives the enable signal, a first electrode connected to the masking control node and a second electrode connected to a second intermediate node; and

a fifth switching element including a control electrode connected to a third input node, a first electrode connected to the second intermediate node and a second electrode which receives a second power voltage,

wherein the second switching element and the third switching element are P-type transistors, and

wherein the fourth switching element and the fifth switching element are N-type transistors.

2 . The gate signal masking circuit of claim 1 , further comprising:

a sixth switching element including a control electrode connected to the output control node, a first electrode which receives the first power voltage and a second electrode connected to a gate output node; and

a seventh switching element including a control electrode connected to the first input node, a first electrode connected to the gate output node and a second electrode which receives the second power voltage.

3 . The gate signal masking circuit of claim 2 , further comprising:

an eighth switching element including a control electrode connected to the masking control node, a first electrode which receives the first power voltage and a second electrode connected to the output control node.

4 . The gate signal masking circuit of claim 2 , further comprising:

a first capacitor including a first electrode connected to the masking control node and a second electrode which receives the second power voltage.

5 . The gate signal masking circuit of claim 1 , wherein a signal of the third input node is an inverted signal of a signal of the second input node.

6 . The gate signal masking circuit of claim 1 , wherein when the enable signal has a high level and a signal of the second input node has a high level, a signal of the masking control node maintains a previous status.

7 . The gate signal masking circuit of claim 1 , wherein when the enable signal has a high level and a signal of the second input node has a low level, a signal of the masking control node has a low level.

8 . The gate signal masking circuit of claim 1 , wherein when the enable signal has a low level and a signal of the second input node has a high level, a signal of the masking control node maintains a previous status.

9 . The gate signal masking circuit of claim 1 , wherein when the enable signal has a low level and a signal of the second input node has a low level, a signal of the masking control node has a high level.

10 . A gate emission driver comprising:

a first driver which generates a carry signal based on a previous carry signal;

a second driver which generates an emission signal based on a previous emission signal; and

a gate signal masking circuit which controls an output of a gate signal based on an enable signal, a signal of a first input node connected to the first driver and a signal of a second input node connected to an emission output node of the second driver and a signal of a third input node connected to the second driver.

11 . The gate emission driver of claim 10 , wherein the gate signal masking circuit comprises:

a first switching element including a control electrode connected to a masking control node, a first electrode connected to the first input node and a second electrode connected to an output control node;

a second switching element including a control electrode connected to the second input node, a first electrode which receives a first power voltage and a second electrode connected to a first intermediate node;

a third switching element including a control electrode which receives the enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the masking control node;

a fourth switching element including a control electrode which receives the enable signal, a first electrode connected to the masking control node and a second electrode connected to a second intermediate node; and

a fifth switching element including a control electrode connected to the third input node, a first electrode connected to the second intermediate node and a second electrode which receives a second power voltage,

wherein the second switching element and the third switching element are P-type transistors, and

wherein the fourth switching element and the fifth switching element are N-type transistors.

12 . The gate emission driver of claim 11 , wherein the gate signal masking circuit further comprises:

a sixth switching element including a control electrode connected to the output control node, a first electrode which receives the first power voltage and a second electrode connected to a gate output node;

a seventh switching element including a control electrode connected to the first input node, a first electrode connected to the gate output node and a second electrode which receives the second power voltage; and

an eighth switching element including a control electrode connected to the masking control node, a first electrode which receives the first power voltage and a second electrode connected to the output control node.

13 . The gate emission driver of claim 11 , wherein the first driver comprises:

a first gate switching element including a control electrode which receives one of a first clock signal and a second clock signal, a first electrode which receives the previous carry signal and a second electrode connected to a first gate node;

a third gate switching element including a control electrode connected to the first gate node, a first electrode which receives the first power voltage and a second electrode connected to a second gate node;

a fourth gate switching element including a control electrode connected to the first gate node, a first electrode connected to the second gate node and a second electrode which receives the second power voltage;

a fifth gate switching element including a control electrode connected to the second gate node, a first electrode which receives the first power voltage and a second electrode connected to a carry output node; and

a sixth gate switching element including a control electrode connected to the second gate node, a first electrode connected to the carry output node and a second electrode which receives the second power voltage,

wherein the first gate switching element, the third gate switching element and the fifth gate switching element are P-type transistors, and

wherein the fourth gate switching element and the sixth gate switching element are N-type transistors.

14 . The gate emission driver of claim 11 , wherein the second driver comprises:

a first emission switching element including a control electrode which receives one of a first clock signal and a second clock signal, a first electrode which receives the previous emission signal and a second electrode connected to a first emission node;

a second emission switching element including a control electrode which receives the other of the first clock signal and the second clock signal, a first electrode which receives the previous emission signal and a second electrode connected to the first emission node;

a third emission switching element including a control electrode connected to the first emission node, a first electrode which receives the first power voltage and a second electrode connected to a second emission node;

a fourth emission switching element including a control electrode connected to the first emission node, a first electrode connected to the second emission node and a second electrode which receives the second power voltage;

a fifth emission switching element including a control electrode connected to the second emission node, a first electrode which receives the first power voltage and a second electrode connected to the emission output node; and

a sixth emission switching element including a control electrode connected to the second emission node, a first electrode connected to the emission output node and a second electrode which receives the second power voltage,

wherein the first emission switching element, the third emission switching element and the fifth emission switching element are P-type transistors, and

wherein the second emission switching element, the fourth emission switching element and the sixth emission switching element are N-type transistors.

15 . The gate emission driver of claim 14 , wherein the second input node is connected to the emission output node, and

wherein the third input node is connected to the second emission node.

16 . The gate emission driver of claim 11 , wherein the second driver comprises:

a first emission switching element including a control electrode which receives one of a first clock signal and a second clock signal, a first electrode which receives the previous emission signal and a second electrode connected to a first emission node;

a third emission switching element including a control electrode connected to the first emission node, a first electrode which receives the first power voltage and a second electrode connected to a second emission node;

a fourth emission switching element including a control electrode connected to the first emission node, a first electrode connected to the second emission node and a second electrode which receives the second power voltage;

a fifth emission switching element including a control electrode connected to the second emission node, a first electrode which receives the first power voltage and a second electrode connected to the emission output node; and

a sixth emission switching element including a control electrode connected to the second emission node, a first electrode connected to the emission output node and a second electrode which receives the second power voltage,

wherein the first emission switching element, the third emission switching element and the fifth emission switching element are P-type transistors, and

wherein the fourth emission switching element and the sixth emission switching element are N-type transistors.

17 . The gate emission driver of claim 11 , wherein the first driver comprises:

a first gate switching element including a control electrode which receives one of a first clock signal and a second clock signal, a first electrode which receives the previous carry signal and a second electrode connected to a first gate node;

a second gate switching element including a control electrode which receives the other of the first clock signal and the second clock signal, a first electrode which receives the previous carry signal and a second electrode connected to the first gate node;

a third gate switching element including a control electrode connected to the first gate node, a first electrode which receives the first power voltage and a second electrode connected to a second gate node;

a fourth gate switching element including a control electrode connected to the first gate node, a first electrode connected to the second gate node and a second electrode which receives the second power voltage;

a fifth gate switching element including a control electrode connected to the second gate node, a first electrode which receives the first power voltage and a second electrode connected to a carry output node; and

a sixth gate switching element including a control electrode connected to the second gate node, a first electrode connected to the carry output node and a second electrode which receives the second power voltage,

wherein the first gate switching element, the third gate switching element and the fifth gate switching element are P-type transistors, and

wherein the second gate switching element, the fourth gate switching element and the sixth gate switching element are N-type transistors.

18 . The gate emission driver of claim 17 , wherein the first input node is connected to the second gate node.

19 . A display apparatus comprising:

a display panel including a pixel;

a gate emission driver which outputs a gate signal and an emission signal to the pixel; and

a data driver which outputs a data voltage to the pixel,

wherein the gate emission driver comprises:

a first driver which generates a carry signal based on a previous carry signal;

a second driver which generates the emission signal based on a previous emission signal; and

a gate signal masking circuit which controls an output of the gate signal based on an enable signal, a signal of a first input node connected to the first driver and a signal of a second input node connected to an emission output node of the second driver and a signal of a third input node connected to the second driver.

20 . The display apparatus of claim 19 , wherein the gate signal masking circuit comprises:

a first switching element including a control electrode connected to a masking control node, a first electrode connected to the first input node and a second electrode connected to an output control node;

a second switching element including a control electrode connected to the second input node, a first electrode which receives a first power voltage and a second electrode connected to a first intermediate node;

a third switching element including a control electrode which receives the enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the masking control node;

a fourth switching element including a control electrode which receives the enable signal, a first electrode connected to the masking control node and a second electrode connected to a second intermediate node; and

a fifth switching element including a control electrode connected to the third input node, a first electrode connected to the second intermediate node and a second electrode which receives a second power voltage,

wherein the second switching element and the third switching element are P-type transistors, and

wherein the fourth switching element and the fifth switching element are N-type transistors.

21 . The display apparatus of claim 20 , wherein the gate signal masking circuit further comprises:

a sixth switching element including a control electrode connected to the output control node, a first electrode which receives the first power voltage and a second electrode connected to a gate output node;

a seventh switching element including a control electrode connected to the first input node, a first electrode connected to the gate output node and a second electrode which receives the second power voltage; and

an eighth switching element including a control electrode connected to the masking control node, a first electrode which receives the first power voltage and a second electrode connected to the output control node.

22 . The display apparatus of claim 20 , wherein the first driver comprises:

a first gate switching element including a control electrode which receives one of a first clock signal and a second clock signal, a first electrode which receives the previous carry signal and a second electrode connected to a first gate node;

a second gate switching element including a control electrode which receives the other of the first clock signal and the second clock signal, a first electrode which receives the previous carry signal and a second electrode connected to the first gate node;

a third gate switching element including a control electrode connected to the first gate node, a first electrode which receives the first power voltage and a second electrode connected to a second gate node;

a fourth gate switching element including a control electrode connected to the first gate node, a first electrode connected to the second gate node and a second electrode which receives the second power voltage;

a fifth gate switching element including a control electrode connected to the second gate node, a first electrode which receives the first power voltage and a second electrode connected to a carry output node; and

a sixth gate switching element including a control electrode connected to the second gate node, a first electrode connected to the carry output node and a second electrode which receives the second power voltage,

wherein the first gate switching element, the third gate switching element and the fifth gate switching element are P-type transistors, and

wherein the second gate switching element, the fourth gate switching element and the sixth gate switching element are N-type transistors.

23 . The display apparatus of claim 22 , wherein the first input node is connected to the second gate node.

24 . The display apparatus of claim 20 , wherein the pixel comprises:

a first pixel switching element including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node and a second electrode connected to a third pixel node;

a second pixel switching element including a control electrode which receives a data writing gate signal, a first electrode which receives the data voltage and a second electrode connected to the second pixel node;

a third pixel switching element including a control electrode which receives a compensation gate signal, a first electrode connected to the first pixel node and a second electrode connected to the third pixel node;

a fourth pixel switching element including a control electrode which receives a data initialization gate signal, a first electrode which receives an initialization voltage and a second electrode connected to the first pixel node;

a fifth pixel switching element including a control electrode which receives the emission signal, a first electrode which receives a pixel high power voltage and a second electrode connected to the second pixel node;

a sixth pixel switching element including a control electrode which receives the emission signal, a first electrode connected to the third pixel node and a second electrode connected to an anode electrode of a light emitting element;

a seventh pixel switching element including a control electrode which receives a light emitting element initialization gate signal, a first electrode which receives a light emitting element initialization voltage and a second electrode connected to the anode electrode of the light emitting element; and

the light emitting element including the anode electrode and a cathode electrode which receives a pixel low power voltage, and

wherein the gate signal is the compensation gate signal.

25 . The display apparatus of claim 20 , wherein the pixel comprises:

a first pixel switching element including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node and a second electrode connected to a third pixel node;

a second pixel switching element including a control electrode which receives a data writing gate signal, a first electrode which receives the data voltage and a second electrode connected to the second pixel node;

a third pixel switching element including a control electrode which receives a compensation gate signal, a first electrode connected to the first pixel node and a second electrode connected to the third pixel node;

a fourth pixel switching element including a control electrode which receives a data initialization gate signal, a first electrode which receives an initialization voltage and a second electrode connected to the first pixel node;

a fifth pixel switching element including a control electrode which receives the emission signal, a first electrode which receives a pixel high power voltage and a second electrode connected to the second pixel node;

a sixth pixel switching element including a control electrode which receives the emission signal, a first electrode connected to the third pixel node and a second electrode connected to an anode electrode of a light emitting element;

a seventh pixel switching element including a control electrode which receives a light emitting element initialization gate signal, a first electrode which receives a light emitting element initialization voltage and a second electrode connected to the anode electrode of the light emitting element; and

the light emitting element including the anode electrode and a cathode electrode which receives a pixel low power voltage, and

wherein the gate signal is the data initialization gate signal.

26 . The display apparatus of claim 20 , wherein the pixel comprises:

a first pixel switching element including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node and a second electrode connected to a third pixel node;

a second pixel switching element including a control electrode which receives a data writing gate signal, a first electrode which receives the data voltage and a second electrode connected to the second pixel node;

a third pixel switching element including a control electrode which receives a compensation gate signal, a first electrode connected to the first pixel node and a second electrode connected to the third pixel node;

a fourth pixel switching element including a control electrode which receives a data initialization gate signal, a first electrode which receives an initialization voltage and a second electrode connected to the first pixel node;

a fifth pixel switching element including a control electrode which receives the emission signal, a first electrode which receives a pixel high power voltage and a second electrode connected to the second pixel node;

a sixth pixel switching element including a control electrode which receives the emission signal, a first electrode connected to the third pixel node and a second electrode connected to an anode electrode of a light emitting element;

a seventh pixel switching element including a control electrode which receives a light emitting element initialization gate signal, a first electrode which receives a light emitting element initialization voltage and a second electrode connected to the anode electrode of the light emitting element; and

the light emitting element including the anode electrode and a cathode electrode which receives a pixel low power voltage,

wherein the light emitting element initialization gate signal is a data writing gate signal of a previous stage, and

wherein the gate signal is one of the compensation gate signal and the data initialization gate signal.

27 . The display apparatus of claim 20 , wherein the pixel comprises:

a first pixel switching element including a control electrode connected to a first pixel node, a first electrode connected to a second pixel node and a second electrode connected to a third pixel node;

a second pixel switching element including a control electrode which receives a data writing gate signal, a first electrode which receives the data voltage and a second electrode connected to the second pixel node;

a third pixel switching element including a control electrode which receives a compensation gate signal, a first electrode connected to the first pixel node and a second electrode connected to the third pixel node;

a fourth pixel switching element including a control electrode which receives a data initialization gate signal, a first electrode which receives an initialization voltage and a second electrode connected to the first pixel node;

a fifth pixel switching element including a control electrode which receives the emission signal, a first electrode which receives a pixel high power voltage and a second electrode connected to the second pixel node;

a sixth pixel switching element including a control electrode which receives the emission signal, a first electrode connected to the third pixel node and a second electrode connected to an anode electrode of a light emitting element;

a seventh pixel switching element including a control electrode which receives a light emitting element initialization gate signal, a first electrode which receives a light emitting element initialization voltage and a second electrode connected to the anode electrode of the light emitting element;

an eighth pixel switching element including a control electrode which receives a bias gate signal, a first electrode which receives a bias voltage and a second electrode connected to the second pixel node, and

the light emitting element including the anode electrode and a cathode electrode which receives a pixel low power voltage, and

wherein the gate signal is one of the compensation gate signal and the data initialization gate signal.